Datasheet

MSP430FR4133, MSP430FR4132, MSP430FR4131
SLAS865B –OCTOBER 2014–REVISED AUGUST 2015 www.ti.com
4.2 Signal Descriptions
Table 4-1 describes the signals for all device variants and package options.
Table 4-1. Signal Descriptions
TERMINAL
PACKAGE SUFFIX I/O DESCRIPTION
NAME
PM G56 G48
General-purpose I/O
P4.7/R13 1 7 7 I/O
Input/output port of third most positive analog LCD voltage V4
General-purpose I/O
P4.6/R23 2 8 8 I/O
Input/output port of second most positive analog LCD voltage V2
General-purpose I/O
P4.5/R33 3 9 9 I/O
Input/output port of first most positive analog LCD voltage V1
General-purpose I/O
P4.4/LCDCAP1 4 10 10 I/O LCD charge pump external port connecting to LCDCAP0 pin by
0.1‑µF capacitor
General-purpose I/O
P4.3/LCDCAP0 5 11 11 I/O LCD charge pump external port connecting to LCDCAP1 pin by
0.1‑µF capacitor
General-purpose I/O
P4.2/XOUT 6 12 12 I/O
Output terminal for crystal oscillator
General-purpose I/O
P4.1/XIN 7 13 13 I/O
Input terminal for crystal oscillator
DVSS 8 14 14 Power ground
DVCC 9 15 15 Power supply
Reset input active low
RST/NMI/SBWTDIO 10 16 16 I/O Nonmaskable interrupt input
Spy-Bi-Wire data input/output
Test Mode pin – selected digital I/O on JTAG pins
TEST/SBWTCK 11 17 17 I
Spy-Bi-Wire input clock
General-purpose I/O
P4.0/TA1.1 12 18 18 I/O
Timer TA1 CCR1 capture: CCI1A input, compare: Out1 outputs
General-purpose I/O
P8.3/TA1.2
(1)
13 19 I/O
Timer TA1 CCR2 capture: CCI2A input, compare: Out2 outputs
General-purpose I/O
P8.2/TA1CLK
(1)
14 20 I/O
Timer clock input TACLK for TA1
General-purpose I/O
P8.1/ACLK/A9
(1)
15 I/O ACLK output
Analog input A9
General-purpose I/O
P8.0/SMCLK/A8
(1)
16 I/O SMCLK output
Analog input A8
General-purpose I/O
(2)
Timer TA0 CCR1 capture: CCI1A input, compare: Out1 outputs
P1.7/TA0.1/TDO/A7 17 21 19 I/O
Test data output
Analog input A7
General-purpose I/O
(2)
Timer TA0 CCR2 capture: CCI2A input, compare: Out2 outputs
P1.6/TA0.2/TDI/TCLK/A6 18 22 20 I/O
Test data input or test clock input
Analog input A6
General-purpose I/O
(2)
Timer clock input TACLK for TA0
P1.5/TA0CLK/TMS/A5 19 23 21 I/O
Test mode select
Analog input A5
(1) Any pin that is not bonded out in a smaller package must be initialized by software after reset to achieve the lowest leakage current.
(2) Because this pin is multiplexed with the JTAG function, TI recommends disabling the pin interrupt function while in JTAG debug to
prevent collisions.
10 Terminal Configuration and Functions Copyright © 2014–2015, Texas Instruments Incorporated
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