Datasheet
SBAS323G − JUNE 2004 − REVISED OCTOBER 2007
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99
Analog Clock (ACLK)
7 6 5 4 3 2 1 0 Reset Value
SFR F6h 0 FREQ6 FREQ5 FREQ4 FREQ3 FREQ2 FREQ1 FREQ0 03h
FREQ6−0 Clock Frequency Selection. This value + 1 divides the system clock to create the ACLK frequency.
bit 6−0 ACLK frequency +
f
CLK
FREQ ) 1
f
MOD
+
f
CLK
(
ACLK ) 1
)
*64
Data Rate +
f
MOD
Decimation
System Reset (SRST)
7 6 5 4 3 2 1 0 Reset Value
SFR F7h 0 0 0 0 0 0 0 RSTREQ 00h
RSTREQ Reset Request. Setting this bit to ‘1’ and then clearing to ‘0’ will generate a system reset.
bit 0
Extended Interrupt Priority (EIP)
7 6 5 4 3 2 1 0 Reset Value
SFR F8h 1 1 1 PWDI PX5 PX4 PX3 PX2 E0h
PWDI Watchdog Interrupt Priority. This bit controls the priority of the watchdog interrupt.
bit 4 0 = The watchdog interrupt is low priority.
1 = The watchdog interrupt is high priority.
PX5 External Interrupt 5 Priority. This bit controls the priority of external interrupt 5.
bit 3 0 = External interrupt 5 is low priority.
1 = External interrupt 5 is high priority.
PX4 External Interrupt 4 Priority. This bit controls the priority of external interrupt 4.
bit 2 0 = External interrupt 4 is low priority.
1 = External interrupt 4 is high priority.
PX3 External Interrupt 3 Priority. This bit controls the priority of external interrupt 3.
bit 1 0 = External interrupt 3 is low priority.
1 = External interrupt 3 is high priority.
PX2 External Interrupt 2 Priority. This bit controls the priority of external interrupt 2.
bit 0 0 = External interrupt 2 is low priority.
1 = External interrupt 2 is high priority.