Datasheet

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 
SBAS323G − JUNE 2004 − REVISED OCTOBER 2007
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Summation 0 (SUMR0)
7 6 5 4 3 2 1 0 Reset Value
SFR E2h 00h
SUMR0 Summation 0. This is the least significant byte of the 32-bit summation register, or bits 0 to 7.
bits 7−0 Write: values in SUMR3−0 are added to the summation register.
Read: clears the Summation Count Interrupt; however, AI in EICON (SFR D8) must also be cleared.
Summation 1 (SUMR1)
7 6 5 4 3 2 1 0 Reset Value
SFR E3h 00h
SUMR1 Summation 1. This is the most significant byte of the lowest 16 bits of the summation register, or bits 8−15.
bits 7−0
Summation 2 (SUMR2)
7 6 5 4 3 2 1 0 Reset Value
SFR E4h 00h
SUMR2 Summation 2. This is the most significant byte of the lowest 24 bits of the summation register, or bits 16−23.
bits 7−0
Summation 3 (SUMR3)
7 6 5 4 3 2 1 0 Reset Value
SFR E5h 00h
SUMR3 Summation 3. This is the most significant byte of the 32-bit summation register, or bits 24−31.
bits 7−0
Offset DAC (ODAC)
7 6 5 4 3 2 1 0 Reset Value
SFR E6h 00h
ODAC Offset DAC. This register will shift the input by up to half of the ADC full-scale input range. The Offset DAC
bits 7−0 value is summed into the ADC prior to conversion. Writing 00h or 80h to ODAC turns off the Offset DAC.. The offset
DAC should be cleared prior to calibration, since the offset DAC analog output is applied directly to the ADC input.
bit 7 Offset DAC Sign bit.
0 = Positive
1 = Negative
bit 6−0
Offset +
*V
REF
2 @ PGA
@
ǒ
ODAC
ƪ
6:0
ƫ
127
Ǔ
@
(
* 1
)
bit7
NOTE: ODAC cannot be used to offset the analog inputs so that the buffer can be used for signals within 50mV of AGND.