Datasheet

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SBAS323G − JUNE 2004 − REVISED OCTOBER 2007
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Accumulator (A or ACC)
7 6 5 4 3 2 1 0 Reset Value
SFR E0h ACC.7 ACC.6 ACC.5 ACC.4 ACC.3 ACC.2 ACC.1 ACC.0 00h
ACC.7−0 Accumulator. This register serves as the accumulator for arithmetic and logic operations.
bits 7−0
Summation/Shifter Control (SSCON)
7 6 5 4 3 2 1 0 Reset Value
SFR E1h SSCON1 SSCON0 SCNT2 SCNT1 SCNT0 SHF2 SHF1 SHF0 00h
The Summation register is powered down when the ADC is powered down. If all zeroes are written to this register, the 32-bit
SUMR3−0 registers will be cleared. The Summation registers will do sign-extend if Bipolar mode is selected in ADCON1.
SSCON1−0 Summation/Shift Count.
bits 7−6
SSCON1 SSCON0 SCNT2 SCNT1 SCNT0 SHF2 SHF1 SHF0 DESCRIPTION
0 0 0 0 0 0 0 0 Clear Summation Register
0 0 0 1 0 0 0 0 CPU Summation on Write to SUMR0 (sum count/shift ignored)
0 0 1 0 0 0 0 0 CPU Subtraction on Write to SUMR0 (sum count/shift ignored)
1 0 x x x Note (1) Note (1) Note (1) CPU Shift only
0 1 Note (1) Note (1) Note (1) x x x ADC Summation only
1 1 Note (1) Note (1) Note (1) Note (1) Note (1) Note (1) ADC Summation completes, then shift completes
(1)
Refer to register bit definition.
SCNT2−0 Summation Count. When the summation is complete an interrupt will be generated unless masked. Reading the
bits 5−3 SUMR0 register clears the interrupt.
SCNT2 SCNT1 SCNT0 SUMMATION COUNT
0 0 0 2
0 0 1 4
0 1 0 8
0 1 1 16
1 0 0 32
1 0 1 64
1 1 0 128
1 1 1 256
SHF2−0 Shift Count.
bits 2−0
SHF2 SHF1 SHF0 SHIFT DIVIDE
0 0 0 1 2
0 0 1 2 4
0 1 0 3 8
0 1 1 4 16
1 0 0 5 32
1 0 1 6 64
1 1 0 7 128
1 1 1 8 256