Datasheet

 
 
SBAS323G − JUNE 2004 − REVISED OCTOBER 2007
www.ti.com
92
ADC Control 1 (ADCON1)
7 6 5 4 3 2 1 0 Reset Value
SFR DDh OF_UF POL SM1 SM0 — CAL2 CAL1 CAL0 0000 0000b
OF_UF Overflow/Underflow. If this bit is set, the data in the summation register is invalid. Either an overflow or underflow
bit 7 occurred. The bit is cleared by writing a ‘0’ to it.
POL Polarity. Polarity of the ADC result and Summation register.
bit 6 0 = Bipolar.
1 = Unipolar. The LSB size is 1/2 the size of bipolar (twice the resolution).
POL ANALOG INPUT DIGITAL OUTPUT
+FSR 7FFFFFh
0
ZERO 000000h
0
−FSR 800000h
+FSR FFFFFFh
1 ZERO 000000h
1
−FSR 000000h
SM1−0 Settling Mode. Selects the type of filter or auto-select which defines the digital filter settling characteristics.
bits 5−4
SM1 SM0 SETTLING MODE
0 0 Auto
0 1 Fast Settling Filter
1 0 Sinc
2
Filter
1 1 Sinc
3
Filter
CAL2−0 Calibration Mode Control Bits.
bits 2−0 Writing to these bits initiates the ADC calibration.
CAL2 CAL1 CAL0 CALIBRATION MODE
0 0 0 No Calibration (default)
0 0 1 Self-Calibration, Offset and Gain
0 1 0 Self-Calibration, Offset only
0 1 1 Self-Calibration, Gain only
1 0 0 System Calibration, Offset only
1 0 1 System Calibration, Gain only
1 1 0 Reserved
1 1 1 Reserved
NOTE
:
Read Value—000b.
ADC Control 2 (ADCON2)
7 6 5 4 3 2 1 0 Reset Value
SFR DEh DR7 DR6 DR5 DR4 DR3 DR2 DR1 DR0 1Bh
DR7−0 Decimation Ratio LSB.
bits 7−0
ADC Control 3 (ADCON3)
7 6 5 4 3 2 1 0 Reset Value
SFR DFh — — — — — DR10 DR9 DR8 06h
DR10−8 Decimation Ratio Most Significant 3 Bits. The ADC output data rate = (ACLK + 1)/64/Decimation Ratio.
bits 2−0