Datasheet

 
 
SBAS323G − JUNE 2004 − REVISED OCTOBER 2007
www.ti.com
9
AC ELECTRICAL CHARACTERISTICS
(1)(2)
: DV
DD
= 2.7V to 5.25V
2.7V to 3.6V 4.75V to 5.25V
SYMBOL FIGURE PARAMETER
MIN
MAX MIN MAX
UNITS
System Clock
f
OSC
(3)
4 External Crystal Frequency (f
OSC
) 1 24 1 33 MHz
1/t
OSC
(3)
4
External Clock Frequency (f
OSC
) at +85°C 0 24 0 40 MHz
1/t
OSC
(3)
4
External Clock Frequency (f
OSC
) at +125°C 0 22 0 36 MHz
f
OSC
(3)
4 External Ceramic Resonator Frequency (f
OSC
) 1 12 1 12 MHz
Program Memory
t
LHLL
1 ALE Pulse Width 1.5t
CLK
− 5 1.5t
CLK
− 5 ns
t
AVLL
1 Address Valid to ALE Low 0.5t
CLK
− 10 0.5t
CLK
− 7 ns
t
LLAX
1 Address Hold After ALE Low 0.5t
CLK
0.5t
CLK
ns
t
LLIV
1 ALE Low to Valid Instruction In 2.5t
CLK
− 35 2.5t
CLK
− 25 ns
t
LLPL
1 ALE Low to PSEN Low 0.5t
CLK
0.5t
CLK
ns
t
PLPH
1 PSEN Pulse Width 2t
CLK
− 5 2t
CLK
− 5 ns
t
PLIV
1 PSEN Low to Valid Instruction In 2t
CLK
− 40 2t
CLK
− 30 ns
t
PXIX
1 Input Instruction Hold After PSEN 5 −5 ns
t
PXIZ
1 Input Instruction Float After PSEN t
CLK
− 5 t
CLK
ns
t
AVIV
1 Address to Valid Instruction In 3t
CLK
− 40 3t
CLK
− 25 ns
t
PLAZ
1 PSEN Low to Address Float 0 0 ns
Data Memory
t
RLRH
2
RD Pulse Width (t
MCS
= 0)
(4)
2t
CLK
− 5 2t
CLK
− 5 ns
t
RLRH
2
RD Pulse Width (t
MCS
> 0)
(4)
t
MCS
− 5 t
MCS
− 5 ns
t
WLWH
3
WR Pulse Width (t
MCS
= 0)
(4)
2t
CLK
− 5 2t
CLK
− 5 ns
t
WLWH
3
WR Pulse Width (t
MCS
> 0)
(4)
t
MCS
− 5 t
MCS
− 5 ns
t
RLDV
2
RD Low to Valid Data In (t
MCS
= 0)
(4)
2t
CLK
− 40 2t
CLK
− 30 ns
t
RLDV
2
RD Low to Valid Data In (t
MCS
> 0)
(4)
t
MCS
− 40 t
MCS
− 30 ns
t
RHDX
2 Data Hold After Read −5 −5 ns
t
RHDZ
2
Data Float After Read (t
MCS
= 0)
(4)
t
CLK
t
CLK
ns
t
RHDZ
2
Data Float After Read (t
MCS
> 0)
(4)
2t
CLK
2t
CLK
ns
t
LLDV
2
ALE Low to Valid Data In (t
MCS
= 0)
(4)
2.5t
CLK
− 40 2.5t
CLK
− 25 ns
t
LLDV
2
ALE Low to Valid Data In (t
MCS
> 0)
(4)
t
CLK
+ t
MCS
− 40 t
CLK
+ t
MCS
− 25 ns
t
AVDV
2
Address to Valid Data In (t
MCS
= 0)
(4)
3t
CLK
− 40 3t
CLK
− 25 ns
t
AVDV
2
Address to Valid Data In (t
MCS
> 0)
(4)
1.5t
CLK
+ t
MCS
−4 0 1.5t
CLK
+ t
MCS
− 25 ns
t
LLWL
2, 3
ALE Low to RD or WR Low (t
MCS
= 0)
(4)
0.5t
CLK
− 5 0.5t
CLK
+ 5 0.5t
CLK
− 5 0.5t
CLK
+ 5 ns
t
LLWL
2, 3
ALE Low to RD or WR Low (t
MCS
> 0)
(4)
t
CLK
− 5 t
CLK
+ 5 t
CLK
− 5 t
CLK
+ 5 ns
t
AVWL
2, 3
Address to RD or WR Low (t
MCS
= 0)
(4)
t
CLK
− 5 t
CLK
− 5 ns
t
AVWL
2, 3
Address to RD or WR Low (t
MCS
> 0)
(4)
2t
CLK
− 5 2t
CLK
− 5 ns
t
QVWX
3 Data Valid to WR Transition −8 −5 ns
t
WHQX
3 Data Hold After WR t
CLK
− 8 t
CLK
− 5 ns
t
RLAZ
2 RD Low to Address Float −0.5t
CLK
− 5 −0.5t
CLK
− 5 ns
t
WHLH
2, 3
RD or WR High to ALE High (t
MCS
= 0)
(4)
−5 5 −5 5 ns
t
WHLH
2, 3
RD or WR High to ALE High (t
MCS
> 0)
(4)
t
CLK
− 5 t
CLK
+ 5 t
CLK
− 5 t
CLK
+ 5 ns
External Clock
t
HIGH
4 High Time
(5)
15 10 ns
t
LOW
4 Low Time
(5)
15 10 ns
t
R
4 Rise Time
(5)
5 5 ns
t
F
4 Fall Time
(5)
5 5 ns
(1)
Parameters are valid over operating temperature range, unless otherwise specified.
(2)
Load capacitance for Port 0, ALE, and PSEN
= 100pF; load capacitance for all other outputs = 80pF.
(3)
t
CLK
= 1/f
OSC
= one oscillator clock period for clock divider = 1.
(4)
t
MCS
is a time period related to the Stretch MOVX selection. The following table shows the value of t
MCS
for each stretch selection:
(5)
These values are characterized, but not 100% production tested.
MD2
MD1 MD0 MOVX DURATION t
MCS
0 0 0
2 Machine Cycles
0
0 0 1
3 Machine Cycles (default)
4t
CLK
0 1 0
4 Machine Cycles
8t
CLK
0 1 1
5 Machine Cycles
12t
CLK
1 0 0
6 Machine Cycles
16t
CLK
1 0 1
7 Machine Cycles
20t
CLK
1 1 0
8 Machine Cycles
24t
CLK
1 1 1
9 Machine Cycles
28t
CLK