Datasheet

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SBAS323G − JUNE 2004 − REVISED OCTOBER 2007
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85
Enable Wake Up (EWU) Waking Up from Idle Mode
7 6 5 4 3 2 1 0 Reset Value
SFR C6h — — — — — EWUWDT EWUEX1 EWUEX0 00h
Auxiliary interrupts will wake up from Idle mode. They are enabled with EAI (EICON.5).
EWUWDT Enable Wake Up Watchdog Timer. Wake using watchdog timer interrupt.
bit 2 0 = Don’t wake up on watchdog timer interrupt.
1 = Wake up on watchdog timer interrupt.
EWUEX1 Enable Wake Up External 1. Wake using external interrupt source 1.
bit 1 0 = Don’t wake up on external interrupt source 1.
1 = Wake up on external interrupt source 1.
EWUEX0 Enable Wake Up External 0. Wake using external interrupt source 0.
bit 0 0 = Don’t wake up on external interrupt source 0.
1 = Wake up on external interrupt source 0.
System Clock Divider (SYSCLK)
7 6 5 4 3 2 1 0 Reset Value
SFR C7h 0 0 DIVMOD1 DIVMOD0 0 DIV2 DIV1 DIV0 00h
NOTE: Changing SYSCLK registers affects all internal clocks, including the ADC clock.
DIVMOD1−0 Clock Divide Mode
bits 5−4 Write:
DIVMOD DIVIDE MODE
00 Normal mode (default, no divide).
01 Immediate mode: start divide immediately; return to Normal mode on Idle mode wakeup condition or by direct write to SFR.
10 Delay mode: same as Immediate mode, except that the mode changes with the millisecond interrupt (MSINT). If MSINT is
enabled, the divide will start on the next MSINT and return to normal mode on the following MSINT. If MSINT is not
enabled, the divide will start on the next MSINT condition (even if masked) but will not leave the divide mode until the
MSINT counter overflows, which follows a wakeup condition. Can exit by directly writing to SFR.
11 Manual mode: start divide immediately; exit mode only by directly writing to SFR. Same as immediate mode, but cannot
return to Normal mode on Idle mode wakeup condition; only by directly writing to SFR.
Read:
DIVMOD DIVISION MODE STATUS
00 No divide
01 Divider is in Immediate mode
10 Divider is in Delay mode
11 Medium mode
DIV2−0 Divide Mode
bit 2−0
DIV DIVISOR f
CLK
FREQUENCY
000 Divide by 2 (default) f
CLK
= f
SYS
/2
001 Divide by 4 f
CLK
= f
SYS
/4
010 Divide by 8 f
CLK
= f
SYS
/8
011 Divide by 16 f
CLK
= f
SYS
/16
100 Divide by 32 f
CLK
= f
SYS
/32
101 Divide by 1024 f
CLK
= f
SYS
/1024
110 Divide by 2048 f
CLK
= f
SYS
/2048
111 Divide by 4096 f
CLK
= f
SYS
/4096