Datasheet

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SBAS323G − JUNE 2004 − REVISED OCTOBER 2007
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7
ELECTRICAL CHARACTERISTICS: AV
DD
= 3V (continued)
All specifications from T
MIN
to T
MAX
, DV
DD
= +2.7V to 5.25V, AV
DD
= +3V, f
MOD
= 15.625kHz, PGA = 1, filter = Sinc
3
, Buffer ON, f
DATA
= 10Hz, Bipolar, f
CLK
= 8MHz,
and V
REF
≡ (REF IN+) − (REF IN−) = +1.25V, unless otherwise noted. For V
DAC
, V
REF
= AV
DD
, R
LOAD
= 10kΩ, and C
LOAD
= 200pF, unless otherwise noted.
MSC1211/12/13/14
PARAMETER UNITSMAXTYPMINCONDITIONS
Voltage DAC Static Performance
(6)
Resolution 16 Bits
Relative Accuracy ±0.05 ±0.146 % of FSR
Differential Nonlinearity Ensured Monotonic by Design ±1 LSB
Zero Code Error All 0s Loaded to DAC Register +13 +35 mV
Full-Scale Error All 1s Loaded to DAC Register −1.25 0 % of FSR
Gain Error −1.25 0 ±1.25 % of FSR
Zero Code Error Drift ±20 µV/°C
Gain Temperature Coefficient ±5 ppm of FSR/°C
Voltage DAC Output Characteristics
(7)
Output Voltage Range AGND AV
DD
V
Output Voltage Settling Time To ±0.003% FSR, 0200h to FD00h 8 µs
Slew Rate 1 V/µs
DC Output Impedance 7 Ω
Short-Circuit Current All 1s Loaded to DAC Register 16 mA
IDAC Output Characteristics
Full-Scale Output Current Maximum V
REF
= 1.25V 25 mA
Maximum Short-Circuit Current Duration Indefinite
Compliance Voltage AV
DD
− 1.5 V
Relative Accuracy Over Full Range 0.185 % of FSR
Zero Code Error 0.5 % of FSR
Full-Scale Error −0.4 % of FSR
Gain Error −0.6 % of FSR
Analog Power-Supply Requirements
Analog Power-Supply Voltage AV
DD
2.7 3.0 3.6 V
Analog Off Current
(8)
Analog OFF, PDCON = 47h < 1 nA
PGA = 1, Buffer OFF 200 µA
ADC Current (I
ADC
)
PGA = 128, Buffer OFF 500 µA
Analog
ADC Current (I
ADC
)
PGA = 1, Buffer ON 240 µA
Analog
Power-Supply
Current
PGA = 128, Buffer ON 850 µA
Power-Supply
Current
VDAC Current (I
VDAC
)
Excluding Load Current, External
Reference
250 µA
V
REF
Supply Current
(I
VDAC
)
ADC ON, V
DAC
OFF 250 µA
(1)
The input impedance for PGA = 128 is the same as that for PGA = 64 (that is, 7MΩ/64).
(2)
Calibration can minimize these errors.
(3)
The gain calibration cannot have a REF IN+ of more than AV
DD
−1.5V with Buffer ON. To calibrate gain, turn Buffer OFF.
(4)
∆V
OUT
is change in digital result.
(5)
9pF switched capacitor at f
SAMP
clock frequency (see Figure 14).
(6)
Linearity calculated using a reduced code range of 512 to 65024; output unloaded.
(7)
Ensured by design and characterization; not production tested.
(8)
Analog Brownout Detect OFF (HCR1.3 = 1), Analog LVD OFF (LVDCON.7 = 1).