Datasheet

 
 
SBAS323G − JUNE 2004 − REVISED OCTOBER 2007
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63
PWM Control (PWMCON)
7 6 5 4 3 2 1 0 Reset Value
SFR A1h — — PPOL PWMSEL SPDSEL TPCNTL2 TPCNTL1 TPCNTL0 00h
PPOL Period Polarity. Specifies the starting level of the PWM pulse.
bit 5 0: ON Period. PWM Duty register programs the ON period.
1: OFF Period. PWM Duty register programs the OFF period.
PWMSEL PWM Register Select. Select which 16-bit register is accessed by PWMLOW/PWMHI.
bit 4 0: Period (must be 0 for TONE mode)
1: Duty
SPDSEL Speed Select.
bit 3 0: 1MHz (the USEC Clock)
1: SYSCLK
TPCNTL Tone Generator/Pulse Width Modulation Control.
bits 2−0
TPCNTL2 TPCNTL1 TPCNTL0 MODE
0 0 0 Disable (default)
0 0 1 PWM
0 1 1 TONE—Square
1 1 1 TONE—Staircase
Tone Low (TONELOW) /PWM Low (PWMLOW)
7 6 5 4 3 2 1 0 Reset Value
SFR A2h
PWM7
TDIV7
PWM6
TDIV6
PWM5
TDIV5
PWM4
TDIV4
PWM3
TDIV3
PWM2
TDIV2
PWM1
TDIV1
PWM0
TDIV0
00h
PWMLOW Pulse Width Modulator Low Bits. These 8 bits are the least significant 8 bits of the PWM register.
bits 7−0
TDIV7−0 Tone Divisor. The low order bits that define the half-time period. For staircase mode the output is high impedance
bits 7−0 for the last 1/4 of this period.
Tone High (TONEHI)/PWM High (PWMHI)
7 6 5 4 3 2 1 0 Reset Value
SFR A3h
PWM15
TDIV15
PWM14
TDIV14
PWM13
TDIV13
PWM12
TDIV12
PWM11
TDIV11
PWM10
TDIV10
PWM9
TDIV9
PWM8
TDIV8
00h
PWMHI Pulse Width Modulator High Bits. These 8 bits are the high order bits of the PWM register.
bits 7−0
TDIV15−8 Tone Divisor. The high order bits that define the half time period. For staircase mode the output is high impedance
bits 7−0 for the last 1/4 of this period.