Datasheet
SBAS323G − JUNE 2004 − REVISED OCTOBER 2007
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58
I
2
C Control (I2CCON) (Available only on the MSC1211 and MSC1213)
7 6 5 4 3 2 1 0 Reset Value
SFR 9Ah START STOP ACK 0 FAST MSTR SCLS FILEN 00h
START Start Condition (Master mode).
bit 7 Read: Current status of start condition or repeated start condition.
Write: When operating as a master, a start condition is transmitted when the START bit is set to 1. During a data
transfer, if the START bit is set, a repeated start is transmitted after the current data transfer is complete. If no transfer
is in progress when the START and STOP bits are set simultaneously, a START will be followed by a STOP.
STOP Stop Condition (Master mode).
bit 6 Read: Current status of stop condition.
Write: Setting STOP to logic 1 causes a stop condition to be transmitted. When a stop condition is received, hardware
clears STOP to logic 0. If both START and STOP are set during a transfer, a stop condition is transmitted followed
by a start condition.
ACK Acknowledge. Defines the ACK/NACK generation from the master/slave receiver during the acknowledge cycle.
bit 5 0: A NACK (high level on SDA) is returned during the acknowledge cycle.
1: An ACK (low level on SDA) is returned during the acknowledge cycle.
In slave transmit mode, 0 = Current byte is last byte, 1 = More to follow.
0 Always set this value to zero.
bit 4
FAST Fast Mode Enable.
bit 3 0: Standard Mode (100kHz)
1: Fast Mode (400kHz)
MSTR SPI Master Mode.
bit 2 0: Slave Mode
1: Master Mode
SCLS Clock Stretch.
bit 1 0: No effect
1: Release the clock line. For the slave mode, the clock is stretched for each data transfer. This bit releases the clock.
FILEN Filter Enable. 50ns glitch filter.
bit 0 0: Filter disabled
1: Filter enabled
SPI Data (SPIDATA) / I
2
C Data (I2CDATA)
7 6 5 4 3 2 1 0 Reset Value
SFR 9Bh 00h
SPIDATA SPI Data. Data for SPI is read from or written to this location. The SPI transmit and receive buffers are
bits 7−0 separate registers, but both are addressed at this location. Read to clear the receive interrupt and write to clear the
transmit interrupt.
I2CDATA I2C Data . (MSC1211 and MSC1213 only.) Data for I
2
C is read from or written to this location. The I
2
C transmit and
receive buffers are separate registers, but both are addressed at this location. Writing to this register
bits 7−0 starts transmission. In Master mode, reading this register starts a Master read cycle.