Datasheet

 
 
SBAS323G − JUNE 2004 − REVISED OCTOBER 2007
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57
SPI Control (SPICON). Any change resets the SPI interface, counters, and pointers.
7 6 5 4 3 2 1 0 Reset Value
SFR 9Ah SCK2 SCK1 SCK0 FIFO ORDER MSTR CPHA CPOL 00h
SCK SCK Selection. Selection of t
CLK
divider for generation of SCK in Master mode.
bits 7−5
SCK2 SCK1 SCK0 SCK PERIOD
0 0 0 t
CLK
/2
0 0 1 t
CLK
/4
0 1 0 t
CLK
/8
0 1 1 t
CLK
/16
1 0 0 t
CLK
/32
1 0 1 t
CLK
/64
1 1 0 t
CLK
/128
1 1 1 t
CLK
/256
FIFO Enable FIFO in On-Chip Indirect Memory.
bit 4 0: Both transmit and receive are double buffers
1: Circular FIFO used for transmit and receive bytes
ORDER Set Bit Order for Transmit and Receive.
bit 3 0: Most Significant Bits First
1: Least Significant Bits First
MSTR SPI Master Mode.
bit 2 0: Slave Mode
1: Master Mode
CPHA Serial Clock Phase Control.
bit 1 0: Valid data starting from half SCK period before the first edge of SCK
1: Valid data starting from the first edge of SCK
CPOL Serial Clock Polarity.
bit 0 0: SCK idle at logic low
1: SCK idle at logic high