Datasheet

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SBAS323G − JUNE 2004 − REVISED OCTOBER 2007
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5
ELECTRICAL CHARACTERISTICS: AV
DD
= 5V (continued)
All specifications from T
MIN
to T
MAX
, DV
DD
= +2.7V to 5.25V, AV
DD
= +5V, f
MOD
= 15.625kHz, PGA = 1, filter = Sinc
3
, Buffer ON, f
DATA
= 10Hz, Bipolar, f
CLK
= 8MHz,
and V
REF
≡ (REF IN+) − (REF IN−) = +2.5V, unless otherwise noted. For V
DAC
, V
REF
= AV
DD
, R
LOAD
= 10kΩ, and C
LOAD
= 200pF, unless otherwise noted.
MSC1211/12/13/14
PARAMETER UNITSMAXTYPMINCONDITIONS
Analog Power-Supply Requirements
Analog Power-Supply Voltage AV
DD
4.75 5 5.25 V
Analog Off Current
(8)
Analog OFF, PDCON = 48h < 1 nA
PGA = 1, Buffer OFF 200 µA
Analog
ADC Current (I
ADC
)
PGA = 128, Buffer OFF 500 µA
Analog
Power-Supply
ADC Current (I
ADC
)
PGA = 1, Buffer ON 240 µA
Power-Supply
Current
PGA = 128, Buffer ON 850 µA
Current
VDAC Current (I
VDAC
) Excluding Load Current, External Reference 250 µA
V
REF
Supply Current
(I
VREF
)
ADC ON, V
DAC
OFF 250 µA
(1)
The input impedance for PGA = 128 is the same as that for PGA = 64 (that is, 7MΩ/64).
(2)
Calibration can minimize these errors.
(3)
The self gain calibration cannot have a REF IN+ of more than AV
DD
−1.5V with Buffer ON. To calibrate gain, turn Buffer OFF.
(4)
∆V
OUT
is change in digital result.
(5)
9pF switched capacitor at f
SAMP
clock frequency (see Figure 14).
(6)
Linearity calculated using a reduced code range of 512 to 65024; output unloaded.
(7)
Ensured by design and characterization; not production tested.
(8)
Analog Brownout Detect OFF (HCR1.3 = 1), Analog LVD OFF (LVDCON.7 = 1).
ELECTRICAL CHARACTERISTICS: AV
DD
= 3V
All specifications from T
MIN
to T
MAX
, DV
DD
= +2.7V to 5.25V, AV
DD
= +3V, f
MOD
= 15.625kHz, PGA = 1, filter = Sinc
3
, Buffer ON, f
DATA
= 10Hz, Bipolar, f
CLK
= 8MHz,
and V
REF
≡ (REF IN+) − (REF IN−) = +1.25V, unless otherwise noted. For V
DAC
, V
REF
= AV
DD
, R
LOAD
= 10kΩ, and C
LOAD
= 200pF, unless otherwise noted.
MSC1211/12/13/14
PARAMETER CONDITIONS MIN TYP MAX UNITS
Analog Inputs (AIN0−AIN7, AINCOM)
Analog Input Range
Buffer OFF AGND − 0.1 AV
DD
+ 0.1 V
Analog Input Range
Buffer ON AGND + 50mV AV
DD
− 1.5 V
Full-Scale Input Voltage Range (AIN+) − (AIN−) ±V
REF
/PGA V
Differential Input Impedance Buffer OFF 7/PGA
(1)
MΩ
Input Current Buffer ON 0.5 nA
Fast Settling Filter −3dB 0.469 • f
DATA
Bandwidth
Sinc
2
Filter −3dB 0.318 • f
DATA
Bandwidth
Sinc
3
Filter −3dB 0.262 • f
DATA
Programmable Gain Amplifier User-Selectable Gain Range 1 128
Input Capacitance Buffer ON 9 pF
Input Leakage Current Multiplexer Channel OFF, T = +25°C 0.5 pA
Burnout Current Sources Sensor Input Open Circuit ±2 µA
(1)
The input impedance for PGA = 128 is the same as that for PGA = 64 (that is, 7MΩ/64).
(2)
Calibration can minimize these errors.
(3)
The gain calibration cannot have a REF IN+ of more than AV
DD
−1.5V with Buffer ON. To calibrate gain, turn Buffer OFF.
(4)
∆V
OUT
is change in digital result.
(5)
9pF switched capacitor at f
SAMP
clock frequency (see Figure 14).
(6)
Linearity calculated using a reduced code range of 512 to 65024; output unloaded.
(7)
Ensured by design and characterization; not production tested.
(8)
Analog Brownout Detect OFF (HCR1.3 = 1), Analog LVD OFF (LVDCON.7 = 1).