Datasheet

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SBAS323G − JUNE 2004 − REVISED OCTOBER 2007
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Hardware Configuration Register 1 (HCR1)
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
CADDR 7Eh DBLSEL1 DBLSEL0 ABLSEL1 ABLSEL0 DAB DDB EGP0 EGP23
NOTE: HCR1 is programmable only in Flash Programming mode, but can be read in User Application mode using the
CADDR and CDATA SFRs or the faddr_data_read Boot ROM routine.
DBLSEL Digital Supply Brownout Level Select
bits 7−6 00: 4.5V
01: 4.2V
10: 2.7V
11: 2.5V (default)
ABLSEL Analog Supply Brownout Level Select
bits 5−4 00: 4.5V
01: 4.2V
10: 2.7V
11: 2.5V (default)
DAB Disable Analog Power-Supply Brownout Reset
bit 3 0: Enable Analog Brownout Reset
1: Disable Analog Brownout Reset (default)
DDB Disable Digital Power-Supply Brownout Reset
bit 2 0: Enable Digital Brownout Reset
1: Disable Digital Brownout Reset (default)
EGP0 Enable General-Purpose I/O for Port 0
bit 1 0: Port 0 is Used for External Memory, P3.6 and P3.7 Used for WR
and RD.
1: Port 0 is Used as General-Purpose I/O (default)
EGP23 Enable General-Purpose I/O for Ports 2 and 3
bit 0 0: Port 2 is Used for External Memory, P3.6 and P3.7. Used for WR
and RD.
1: Port 2 and Port3 are Used as General-Purpose I/O (default)
Configuration Memory Programming
Hardware Configuration Memory can be changed only in Serial Flash Programming mode or Parallel Programming mode.