Datasheet

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SBAS323G − JUNE 2004 − REVISED OCTOBER 2007
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Hardware Configuration Register 0 (HCR0)—Accessed Using SFR Registers CADDR and CDATA.
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
CADDR 7Fh EPMA PML RSL EBR EWDR DFSEL2 DFSEL1 DFSEL0
NOTE: HCR0 is programmable only in Flash Programming mode, but can be read in User Application mode using the
CADDR and CDATA SFRs or the faddr_data_read Boot ROM routine.
EPMA Enable Programming Memory Access (Security Bit).
bit 7 0: After reset in programming modes, Flash Memory can only be accessed in UAM until a mass erase is done.
1: Fully Accessible (default)
PML Program Memory Lock (PML has priority over RSL).
bit 6 0: Enable writing to Program Memory in UAM.
1: Disable writing to Program Memory in UAM (default).
RSL Reset Sector Lock. The reset sector can be used to provide another method of Flash Memory programming, which
bit 5 allows Program Memory updates without changing the jumpers for in-circuit code updates or program development.
The code in this boot sector would then provide the monitor and programming routines with the ability to jump into
the main Flash code when programming is finished.
0: Enable Reset Sector Writing
1: Enable Read-Only Mode for Reset Sector (4kB) (default)
EBR Enable Boot ROM. Boot ROM is 2kB of code located in ROM, not to be confused with the 4kB Boot Sector located
bit 4 in Flash Memory.
0: Disable Internal Boot ROM
1: Enable Internal Boot ROM (default)
EWDR Enable Watchdog Reset.
bit 3 0: Disable Watchdog Reset
1: Enable Watchdog Reset (default)
DFSEL1−0 Data Flash Memory Size (see Table 4 and Table 5).
bits 2−0 000: Reserved
001: 32kB, 16kB, 8kB, or 4kB Data Flash Memory
010: 16kB, 8kB, or 4kB Data Flash Memory
011: 8kB or 4kB Data Flash Memory
100: 4kB Data Flash Memory
101: 2kB Data Flash Memory
110: 1kB Data Flash Memory
111: No Data Flash Memory (default)