Datasheet

 
 
SBAS323G − JUNE 2004 − REVISED OCTOBER 2007
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31
BIPOLAR OPERATION USING THE DAC
The DAC can be used for a bipolar output range, as shown
in Figure 18; the circuit illustrates an output voltage range
of ±V
REF
. Rail-to-rail operation at the amplifier output is
achievable using an OPA703 as the output amplifier.
V
REF
VDAC
R
1
100kΩ
R
2
100kΩ
OPA703
DAC
REF
±(DAC
REF
)
+6V
−6V
Figure 18. Bipolar Operation with the DAC
The output voltage for any input code can be calculated as
follows:
V
O
+
ƪ
DAC
REF
@
ǒ
D
65536
Ǔ
@
ǒ
R
1
)R
2
R
1
Ǔ
* DAC
REF
@
ǒ
R
1
R
2
Ǔ
ƫ
where D represents the input code in decimal (0 to 65535).
With DAC
REF
= 5V, R
1
= R
2
:
V
O
+
ǒ
10 @ D
65536
Ǔ
* 5V
This is an output voltage range of ±5V with 0000h
corresponding to a –5V output and FFFFh corresponding
to a +5V output. Similarly, using DAC
REF
= 2.5V, a ±2.5V
output voltage can be achieved.
IDAC
The IDAC can source current and sink current (through an
external transistor). The compliance specification of the
IDAC output defines the maximum output voltage to
achieve the expected current.
IDAC
OUT
+
ȧ
ȧ
ȥ
ȡ
Ȣ
4 @ V
DAC
R
DAC
for Source mode
V
DAC
R
DAC
for Sink mode
with V
DAC
< (AV
DD
− 2V) for maximum code.
Refer to Figure 17 for the IDAC structure.
ANALOG/DIGITAL LOW-VOLTAGE DETECT
The MSC1211/12/13/14 contain an analog or digital
low-voltage detect. When the analog or digital supply
drops below the value programmed in LVDCON (SFR
E7h), an interrupt is generated (one for each supply).
RESET
The device can be reset from the following sources:
D Power-on reset
D External reset
D Software reset
D Watchdog timer reset
D Brownout reset
An external reset is accomplished by taking the RST pin
high for two t
OSC
periods, followed by taking the RST pin
low. A software reset is accomplished through the System
Reset register (SRTST, 0F7h). A watchdog timer reset is
enabled and controlled through Hardware Configuration
Register 0 (HCR0) and the Watchdog Timer register
(WDTCON, 0FFh). A brownout reset is enabled through
Hardware Configuration Register 1 (HCR1). External
reset, software reset, and watchdog timer reset complete
after 2
17
clock cycles. A brownout reset completes after 2
15
clock cycles.
All sources of reset cause the digital pins to be pulled high
from the initiation of the reset. For an external reset, taking
the RST pin high stops device operation (crystal
oscillation, internal oscillator, or PLL circuit operation) and
causes all digital pins to be pulled high from that point.
Taking the RST pin low initiates the reset procedure.
A recommended external reset circuit is shown in
Figure 19. The serial 10kΩ resistor is recommended for
any external reset circuit configuration.
10k
Ω
13 RST
MSC1211/12/13/14
0.1
µ
F
1M
Ω
DV
DD
Figure 19. Typical Reset Circuit