Datasheet

 
 
SBAS323G − JUNE 2004 − REVISED OCTOBER 2007
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30
VDAC
The architecture of the MSC1211/12/13/14 consists of a
string DAC followed by an output buffer amplifier.
Figure 17 shows a block diagram of the DAC architecture.
The input coding to the DAC is straight binary, so the ideal
output voltage is given by:
VDAC + V
REF
@
ǒ
D
65536
Ǔ
where D = decimal equivalent of the binary code that is
loaded to the DAC register; it can range from 0 to 65535.
DAC RESISTOR STRING
The DAC selects the voltage from a string of resistors from
the reference to AGND. It is essentially a string of resistors,
each of value R. The code loaded into the DAC register
determines at which node on the string the voltage is
tapped off to be fed into the output amplifier by closing one
of the switches connecting the string to the amplifier. It is
ensured monotonic because of the design architecture.
DAC OUTPUT AMPLIFIER
The output buffer amplifier is capable of generating
rail-to-rail voltages on its output, which provides an output
range of AGND to AV
DD
. It is capable of driving a load of
2kΩ in parallel with 1000pF to GND. The source and sink
capabilities of the output amplifier can be seen in the
typical curves. The slew rate is 1V/µs with a full-scale
settling time of 8µs.
DAC REFERENCE
Each DAC can be selected to use the REFOUT/REF IN+
pin voltage or the supply voltage AV
DD
as the reference for
the DAC.
DAC LOADING
The DAC can be selected to be turned off with a 1kΩ,
100kΩ, or open circuit on the DAC outputs.
DAC3
DAC2
DAC1
DAC0
21 AIN3/VDAC3
AIN2/VDAC2
VDAC1
VDAC0
DAC
Sink
Connection
AIN0/IDAC0
RDAC0
AIN1/IDAC1
RDAC1
20
31
19
32
17
Current
Mirror
Current
Mirror
18
16
Sink
Source
Sink
Source
REFOUT/
REF IN+
AV
DD
30
REF
2.5V/1.25V
28
0.1
µ
F
Figure 17. DAC Architecture