Datasheet

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SBAS323G − JUNE 2004 − REVISED OCTOBER 2007
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ADC PGA
The PGA can be set to gains of 1, 2, 4, 8, 16, 32, 64, or 128.
Using the PGA can actually improve the effective
resolution of the ADC. For instance, with a PGA of 1 on a
±2.5V full-scale range (FSR), the ADC can resolve to
1.5µV. With a PGA of 128 on a ±19mV FSR, the ADC can
resolve to 75nV, as shown in Table 3.
Table 3. Sampling Frequency versus PGA Setting
PGA
SETTING
BIPOLAR MODE
FULL-SCALE
RANGE (V)
ENOB
(1)
AT 10HZ
RMS
INPUT-REFERRED
NOISE (nV)
1 ±2.5V 21.7 1468
2 ±1.25 21.5 843
4 ±0.625 21.4 452
8 ±0.313 21.2 259
16 ±0.156 20.8 171
32 ±0.0781 20.4 113
64 ±0.039 20 74.5
128 ±0.019 19 74.5
(1)
ENOB = Log
2
(FSR/RMS Noise) = Log
2
(2
24
) − Log
2
(σ
CODES
)
= 24 − Log
2
(σ
CODES
)
ADC OFFSET DAC
The analog input to the PGA can be offset (in bipolar mode)
by up to half the full-scale input range of the PGA by using
the ODAC register (SFR E6h). The ODAC (Offset DAC)
register is an 8-bit value; the MSB is the sign and the seven
LSBs provide the magnitude of the offset. Since the ODAC
introduces an analog (instead of digital) offset to the PGA,
using the ODAC does not reduce the range of the ADC.
ADC MODULATOR
The modulator is a single-loop, 2nd-order system. The
modulator runs at a clock speed (f
MOD
) that is derived from
the CLK using the value in the Analog Clock (ACLK)
register (SFR F6
h). The data output rate is:
Data Rate + f
DATA
+
f
MOD
Decimation Ratio
where f
MOD
+
f
CLK
(ACLK ) 1) @ 64
+
f
ACLK
64
and Decimation Ratio is set in [ADCON3:ADCON2].
ADC CALIBRATION
The offset and gain errors in the MSC1211/12/13/14, or the
complete system, can be reduced with calibration.
Calibration is controlled through the ADCON1 register
(SFR DDh), bits CAL2:CAL0. Each calibration process
takes seven t
DATA
periods (data conversion time) to
complete. Therefore, it takes 14 t
DATA
periods to complete
both an offset and gain calibration.
For system calibration, the appropriate signal must be
applied to the inputs. The system offset calibration
requires a zero input signal. It then computes an offset that
will nullify offset in the system. The system gain calibration
requires a positive full-scale input signal. It then computes
a value to nullify gain errors in the system. Each of these
calibrations will take seven t
DATA
periods to complete.
Calibration should be performed after power on. It should
also be done after a change in temperature, decimation
ratio, buffer, Power Supply, voltage reference, or PGA.
The Offset DAC wil affect offset calibration; therefore, the
value of the Offset DAC should be zero until prior to
performing a calibration.
At the completion of calibration, the ADC Interrupt bit goes
high, which indicates the calibration is finished and valid
data is available.
ADC DIGITAL FILTER
The Digital Filter can use either the Fast Settling, Sinc
2
, or
Sinc
3
filter, as shown in Figure 15. In addition, the Auto
mode changes the Sinc filter after the input channel or
PGA is changed. When switching to a new channel, it will
use the Fast Settling filter for the next two conversions, the
first of which should be discarded.
Adjustable Digital Filter
Data Out
Modulator
Fast Settling
Sinc
2
Sinc
3
Fast Fast Sinc
2
Sinc
3
1 2 3 4
FILTER
SETTLING TIME
(Conversion Cycles)
(1)
Sinc
3
Sinc
2
Fast
3
2
1
NOTE: (1) MUX change may add one cycle.
CONVERSION CYCLE
AUTO MODE FILTER SELECTION
FILTER SETTLING TIME
Figure 15. Filter Step Responses