Datasheet

 
 
SBAS323G − JUNE 2004 − REVISED OCTOBER 2007
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27
AIN3
AIN4
AIN5
AIN6
AIN0
AIN1
AIN2
AIN7
AINCOM
AGND
Buffer
I
In+
Burnout Detect (2µA)
Burnout Detect (2µA)
Temperature Sensor
80 • I
AV
DD
AV
DD
AV
DD
In−
Figure 13. Input Multiplexer Configuration
ADC INPUT BUFFER
The analog input impedance is always high, regardless of
PGA setting (when the buffer is enabled). With the buffer
enabled, the input voltage range is reduced and the analog
power-supply current is higher. If the limitation of input
voltage range is acceptable, then the buffer is always
preferred. The input impedance of the MSC1211/12/13/14
without the buffer is 7MΩ/PGA. The buffer is controlled by
the state of the BUF bit in the ADC control register (ADCON0
DCh).
ADC ANALOG INPUT
When the buffer is not selected, the input impedance of the
analog input changes with ACLK clock frequency (ACLK
F6h) and gain (PGA). The relationship is:
Impedance (W) +
1
f
SAMP
@ C
S
A
IN
Impedance (W) +
ǒ
1 10
6
ACLK Frequency
Ǔ
@
ǒ
7MW
PGA
Ǔ
where ACLK frequency (f
ACLK
) +
f
CLK
ACLK ) 1
and modclk + f
MOD
+
f
ACLK
64
.
NOTE
:
The input impedance for PGA = 128 is the same as
that for PGA = 64 (
that is,
7MW
64
).
Figure 14 shows the basic input structure of the
MSC1211/12/13/14. The sampling frequency varies
according to the PGA settings, as shown in the table in
Figure 14.
BIPOLAR MODE UNIPOLAR MODE
PGA FULL-SCALE RANGE FULL-SCALE RANGE f
SAMP
1 ±V
REF
+V
REF
f
MOD
2 ±V
REF
/2 +V
REF
/2 f
MOD
4 ±V
REF
/4 +V
REF
/4 f
MOD
8 ±V
REF
/8 +V
REF
/8 f
MOD
S 2
16 ±V
REF
/16 +V
REF
/16 f
MOD
S 4
32 ±V
REF
/32 +V
REF
/32 f
MOD
S 8
64 ±V
REF
/64 +V
REF
/64 f
MOD
S 16
128 ±V
REF
/128 +V
REF
/128 f
MOD
S 16
NOTE
:
f
MOD
= ACLK frequency/64
R
SWITCH
(3k typical)
Sampling
Frequency = f
SAMP
High
Impedance
>1G
Ω
C
S
AGND
A
IN
(9pF typical)
PGA C
S
1 9pF
2 18pF
4 to 128 36pF
Figure 14. Analog Input Structure