Datasheet
SBAS323G − JUNE 2004 − REVISED OCTOBER 2007
www.ti.com
25
Furthermore, improvements were made to peripheral
features that off-load processing from the core, and the
user, to further improve efficiency. For instance, the SPI
interface uses a FIFO, which allows the SPI interface to
transmit and receive data with minimum overhead needed
from the core. Also, a 32-bit accumulator was added to
significantly reduce the processing overhead for multiple
byte data from the ADC or other sources. This allows for
32-bit addition, subtraction and shifting to be
accomplished in a few instruction cycles, compared to
hundreds of instruction cycles executed through software
implementation.
Family Device Compatibility
The hardware functionality and pin configuration across
the MSC1211/12/13/14 families are fully compatible. To
the user, the only differences between family members are
the memory configuration, the number of DACs, and the
availability of I
2
C for the MSC1211 and MSC1213. This
design makes migration between family members simple.
This gives the user the ability to add or subtract software
functions and to freely migrate between family members.
Thus, the MSC1211/12/13/14 can become a standard
device used across several application platforms.
Family Development Tools
The MSC1211/12/13/14 are fully compatible with the
standard 8051 instruction set. This compatibility means
that users can develop software for the
MSC1211/12/13/14 with their existing 8051 development
tools. Additionally, a complete, integrated development
environment is provided with each demo board, and
third-party developers also provide support.
Power-Down Modes
The MSC1211/12/13/14 can each power several of the
on-chip peripherals and put the CPU into Idle mode. This
is accomplished by shutting off the clocks to those
sections, as shown in Figure 11.
(see Figure 14)
USEC
FB
MSECH
HMSEC
FE
MSINT
FA
ACLK
F6
divide
by 64
divide
by 4
MSECL
FD
FC
ms
µ
s
100ms
Flash Write
Timing
Flash Erase
Timing
WDTCON
SECINT
F9
FF
FTCON
[3:0]
FTCON
[7:4]
EF
EF
seconds
interrupt
watchdog
interrupt
milliseconds
interrupt
ADC Output Rate
ADCON3 ADCON2
DF DE
Decimation Ratio
SPICON/
I2CCON
(1)
9A
SCL/SCK
f
CLK
f
SYS
(30
µ
sto40
µ
s)
(5ms to 11ms)
PDCON.0
PDCON.1
PDCON.2
PDCON.3
IDLE
CPUClock
Timers 0/1/2
SYSCLK
Analog Power Down
USART 0/1
REF
CLOCK
REFCLK
SEL
f
ACLK
f
DATA
f
SAMP
f
MOD
f
CLK
STOP
f
OSC
C7
PDCON.4
PWMHI PWMLOW
A3 A2
PWM Clock
ADCON0
DC
DC
NOTE: (1) I2CCON only available on the MSC1211 and MSC1213.
Figure 11. MSC1211/12/13/14 Timing Chain and Clock Control