Datasheet

 
 
SBAS323G − JUNE 2004 − REVISED OCTOBER 2007
www.ti.com
15
PIN DESCRIPTIONS (continued)
PIN # DESCRIPTIONNAME
44 PSEN
OSCCLK
MODCLK
Program Store Enable: Connected to optional external memory as a chip enable. PSEN will provide an active low pulse.
In programming mode, PSEN
is used as an input along with ALE to define serial or parallel programming mode.
PSEN
is held high for parallel programming and held low for serial programming. This pin can also be selected (when not
using external memory) to output the Oscillator clock, Modulator clock, high, or low. Care should be taken so that loading
on this pin should not inadvertently cause the device to enter programming mode.
ALE PSEN Program Mode Selection During Reset
NC NC Normal operation (User Application mode)
0 NC Parallel programming
NC 0 Serial programming
0 0 Reserved
45 ALE Address Latch Enable: Used for latching the low byte of the address during an access to external memory. ALE is emitted at
a constant rate of 1/4 the oscillator frequency, and can be used for external timing or clocking. One ALE pulse is skipped
during each access to external data memory. In programming mode, ALE is used as an input along with PSEN
to define
serial or parallel programming mode. ALE is held high for serial programming and held low for parallel programming. This pin
can also be selected (when not using external memory) to output high or low. Care should be taken so that loading on this
pin should not inadvertently cause the device to enter programming mode.
48 EA External Access Enable: EA must be externally held low to enable the device to fetch code from external program
memory locations starting with 0000h. No internal pull-up on this pin.
46, 47, 49-54 P0.0-P0.7 Port 0 is a bidirectional I/O port. The alternate functions for Port 0 are listed below.
46, 47, 49-54
P0.0-P0.7
Port Alternate Name Alternate Use
P0.0 AD0 Address/Data bit 0
P0.1 AD1 Address/Data bit 1
P0.2 AD2 Address/Data bit 2
P0.3 AD3 Address/Data bit 3
P0.4 AD4 Address/Data bit 4
P0.5 AD5 Address/Data bit 5
P0.6 AD6 Address/Data bit 6
P0.7 AD7 Address/Data bit 7
55, 56, 59-64 P1.0-P1.7 Port 1 is a bidirectional I/O port. The alternate functions for Port 1 are listed below. Refer to P1DDR, SFR AEh−AFh.
55, 56, 59-64
P1.0-P1.7
Port Alternate Name(s) Alternate Use
P1.0 T2 T2 input
P1.1 T2EX T2 external input
P1.2 RxD1 Serial port input
P1.3 TxD1 Serial port output
P1.4 INT2/SS External Interrupt / Slave Select
P1.5 INT3/MOSI External Interrupt / Master Out-Slave In
P1.6 INT4/MISO/SDA
(1)
External Interrupt / Master In-Slave Out / SDA
P1.7 INT5/SCK/SCL
(1)
External Interrupt / Serial Clock
(1)
SDA and SCL are only available on the MSC1213.