Datasheet

 
 
SBAS323G − JUNE 2004 − REVISED OCTOBER 2007
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12
RESET AND POWER-ON TIMING
t
RW
t
RS
t
RH
t
RFD
t
RFD
RST
PSEN
ALE
NOTE: PSEN and ALE are internally pulled up with ~9kΩduring RST high.
EA
t
RRD
t
RRD
Figure 5. Reset Timing, User Application Mode
t
RFD
PSEN
ALE
NOTE: PSEN and ALE are internally pulled up with ~9k
Ω
during RST high.
t
RW
RST
t
RS
t
RH
t
RRD
t
RRD
Figure 6. Parallel Flash Programming Power-On Timing (EA is ignored)
t
RFD
PSEN
ALE
NOTE: PSEN and ALE are internally pulled up with ~9k
Ω
during RST high.
t
RW
RST
t
RS
t
RH
t
RRD
t
RRD
Figure 7. Serial Flash Programming Power-On Timing (EA is ignored)
Table 1. Serial/Parallel Flash Programming Timing
SYMBOL PARAMETER MIN MAX UNIT
t
RW
RST width 2t
OSC
— —
t
RRD
RST rise to PSEN ALE internal pull high — 5 µs
t
RFD
RST falling to PSEN and ALE start — (2
17
+ 512)t
OSC
—
t
RS
Input signal to RST falling setup time t
OSC
— —
t
RH
RST falling to input signal hold time (2
17
+ 512)t
OSC
— —