Datasheet

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SBAS323G − JUNE 2004 − REVISED OCTOBER 2007
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101
One Millisecond Timer High Byte (MSECH)
7 6 5 4 3 2 1 0 Reset Value
SFR FDh MSECH7 MSECH6 MSECH5 MSECH4 MSECH3 MSECH2 MSECH1 MSECH0 0Fh
MSECH7−0 One Millisecond Timer High Byte. This value in combination with the previous register is used to create a 1ms clock.
bits 7−0 1ms = (MSECH • 256 + MSECL + 1) • t
CLK
.
One Hundred Millisecond Timer (HMSEC)
7 6 5 4 3 2 1 0 Reset Value
SFR FEh WRT HMSEC6 HMSEC5 HMSEC4 HMSEC3 HMSEC2 HMSEC1 HMSEC0 63h
WRT Write Control. Determines whether to write the value immediately or wait until the current count is finished. Read = 0.
bit 7 0 = Delay Write Operation. The MSINT value is loaded when the current count expires.
1 = Write Immediately. The MSINT counter is loaded once the CPU completes the write operation.
HMSEC6−0 One Hundred Millisecond. This clock divides the 1ms clock to create a 100ms clock.
bits 6−0 100ms = (MSECH • 256 + MSECL + 1) • (HMSEC + 1) • t
CLK
.
Watchdog Timer (WDTCON)
7 6 5 4 3 2 1 0 Reset Value
SFR FFh EWDT DWDT RWDT WDCNT4 WDCNT3 WDCNT2 WDCNT1 WDCNT0 00h
EWDT Enable Watchdog (R/W).
bit 7 Write 1/Write 0 sequence sets the Watchdog Enable Counting bit.
DWDT Disable Watchdog (R/W).
bit 6 Write 1/Write 0 sequence clears the Watchdog Enable Counting bit.
RWDT Reset Watchdog (R/W).
bit 5 Write 1/Write 0 sequence restarts the Watchdog Counter.
WDCNT4−0 Watchdog Count (R/W).
bits 4−0 Watchdog expires in (WDCNT + 1) • HMSEC to (WDCNT + 2) • HMSEC, if the sequence is not asserted. There is
an uncertainty of 1 count.