Datasheet

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 
SBAS323G − JUNE 2004 − REVISED OCTOBER 2007
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Port 0 Data Direction Low (P0DDRL)
7 6 5 4 3 2 1 0 Reset Value
SFR ACh P03H P03L P02H P02L P01H P01L P00H P00L 00h
P0.3 Port 0 Bit 3 Control.
bits 7−6
P03H P03L
0 0 Standard 8051 (Pull-Up)
0 1 CMOS Output
1 0 Open Drain Output
1 1 Input
P0.2 Port 0 Bit 2 Control.
bits 5−4
P02H P02L
0 0 Standard 8051 (Pull-Up)
0 1 CMOS Output
1 0 Open Drain Output
1 1 Input
P0.1 Port 0 Bit 1 Control.
bits 3−2
P01H P01L
0 0 Standard 8051 (Pull-Up)
0 1 CMOS Output
1 0 Open Drain Output
1 1 Input
P0.0 Port 0 Bit 0 Control.
bits 1−0
P00H P00L
0 0 Standard 8051 (Pull-Up)
0 1 CMOS Output
1 0 Open Drain Output
1 1 Input
NOTE: Port 0 also controlled by EA and Memory Access Control HCR1.EGP0.