Datasheet
SBAS323G − JUNE 2004 − REVISED OCTOBER 2007
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62
I
2
C Start (I2CSTART) (Available only on the MSC1211 and MSC1213)
7 6 5 4 3 2 1 0 Reset Value
SFR 9Eh 80h
I2CSTART I
2
C Start. Write-only. When any value is written to this register, the I
2
C system is reset; that is, the counters
bits 7−0 and state machines will go back to the initial state. So, in multi-master mode when arbitration is lost, then the I
2
C
should be reset so that the counters and finite state machines (FSMs) are brought back to the idle state.
SPI Buffer Start Address (SPISTART)
7 6 5 4 3 2 1 0 Reset Value
SFR 9Eh 1 80h
SPISTART SPI FIFO Start Address. Write-only. This specifies the start address of the SPI data buffer. This is a circular FIFO
bits 6−0 that is located in the 128 bytes of indirect RAM. The FIFO starts at this address and ends at the address specified
in SPIEND. Must be less than SPIEND. Writing clears SPI transmit and receive counters.
SPITP SPI Transmit Pointer. Read-only. This is the FIFO address for SPI transmissions. This is where the next byte will
bits 6−0 be written into the byte will be written into the SPI FIFO buffer. This pointer increments after each write to the SPI Data
register unless that would make it equal to the SPI Receive pointer.
SPI Buffer End Address (SPIEND)
7 6 5 4 3 2 1 0 Reset Value
SFR 9Fh 1 80h
SPIEND SPI FIFO End Address. Write-only. This specifies the end address of the SPI data FIFO. This is a circular buffer that
bits 6−0 is located in the 128 bytes of indirect RAM. The buffer starts at SPISTART and ends at this address.
SPIRP SPI Receive Pointer. Read-only. This is the FIFO address for SPI received bytes. This is the location of the next byte
bits 6−0 to be read from the SPI FIFO. This increments with each read from the SPI Data register until the RxCNT is zero.
Port 2 (P2)
7 6 5 4 3 2 1 0 Reset Value
SFR A0h FFh
P2 Port 2. This port functions as an address bus during external memory access, and as a general-purpose I/O port.
bits 7−0 During external memory cycles, this port will contain the MSB of the address. Whether Port 2 is used as
general-purpose I/O or for external memory access is determined by the Flash Configuration Register (HCR1.0).