Datasheet

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SBAS323G − JUNE 2004 − REVISED OCTOBER 2007
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59
SPI Receive Control (SPIRCON)
7 6 5 4 3 2 1 0 Reset Value
SFR 9Ch
RXCNT7
RXFLUSH
RXCNT6 RXCNT5 RXCNT4 RXCNT3
RXCNT2
RXIRQ2
RXCNT1
RXIRQ1
RXCNT0
RXIRQ0
00h
RXCNT Receive Counter. Read-only bits which read the number of bytes in the receive buffer (0 to 128).
bits 7−0
RXFLUSH Flush Receive FIFO. Write-only.
bit 7 0: No Action
1: SPI Receive Buffer Set to Empty
RXIRQ Read IRQ Level. Write-only.
bits 2−0
000 Generate IRQ when Receive Count = 1 or more.
001 Generate IRQ when Receive Count = 2 or more.
010 Generate IRQ when Receive Count = 4 or more.
011 Generate IRQ when Receive Count = 8 or more.
100 Generate IRQ when Receive Count = 16 or more.
101 Generate IRQ when Receive Count = 32 or more.
110 Generate IRQ when Receive Count = 64 or more.
111 Generate IRQ when Receive Count = 128 or more.
I
2
C GM (I2CGM) (Available only on the MSC1211 and MSC1213)
7 6 5 4 3 2 1 0 Reset Value
SFR 9Ch GCMEN 00h
GCMEN General Call/Multiple Master Enable. Write-only.
bit 7 Slave mode: 0 = General call ignored, 1 = General call will be detected
Master mode: 0 = Single master, 1 = Multiple master mode