Datasheet

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SBAS323G − JUNE 2004 − REVISED OCTOBER 2007
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External Interrupt Flag (EXIF)
7 6 5 4 3 2 1 0 Reset Value
SFR 91h IE5 IE4 IE3 IE2 1 0 0 0 08h
IE5 External Interrupt 5 Flag. This bit will be set when a falling edge is detected on INT5. This bit must be cleared
bit 7 manually by software. Setting this bit in software will cause an interrupt if enabled.
IE4 External Interrupt 4 Flag. This bit will be set when a rising edge is detected on INT4. This bit must be cleared
bit 6 manually by software. Setting this bit in software will cause an interrupt if enabled.
IE3 External Interrupt 3 Flag. This bit will be set when a falling edge is detected on INT3
. This bit must be cleared
bit 5 manually by software. Setting this bit in software will cause an interrupt if enabled.
IE2 External Interrupt 2 Flag. This bit will be set when a rising edge is detected on INT2. This bit must be cleared
bit 4 manually by software. Setting this bit in software will cause an interrupt if enabled.
Memory Page (MPAGE)
7 6 5 4 3 2 1 0 Reset Value
SFR 92h 00h
MPAGE The 8051 uses Port 2 for the upper 8 bits of the external Data Memory access by MOVX A@Ri and MOVX @Ri, A
bits 7−0 instructions. The MSC1211/12/13/14 uses register MPAGE instead of Port 2. To access external Data Memory using
the MOVX A@Ri and MOVX @Ri, A instructions, the user should preload the upper byte of the address into MPAGE
(versus preloading into P2 for the standard 8051).
Configuration Address (CADDR) (write-only)
7 6 5 4 3 2 1 0 Reset Value
SFR 93h 00h
CADDR Configuration Address. This register supplies the address for reading bytes in the 128 bytes of Flash
bits 7−0 Configuration Memory. It is recommended that faddr_data_read be used when accessing Configuration Memory.
CAUTION:If this register is written to while executing from Flash Memory, the CDATA register will be incorrect.
Configuration Data (CDATA)
7 6 5 4 3 2 1 0 Reset Value
SFR 94h 00h
CDATA Configuration Data. This register will contain the data in the 128 bytes of Flash Configuration Memory that
bits 7−0 is located at the last written address in the CADDR register. This is a read-only register.
Memory Control (MCON)
7 6 5 4 3 2 1 0 Reset Value
SFR 95h BPSEL 0 0 — — — — RAMMAP 00h
BPSEL Breakpoint Address Selection
bit 7 Write: Select one of two Breakpoint registers: 0 or 1.
0: Select breakpoint register 0.
1: Select breakpoint register 1.
Read: Provides the Breakpoint register that created the last interrupt: 0 or 1.
RAMMAP Memory Map 1kB extended SRAM.
bit 0 0: Address is: 0000h—03FFh (default) (Data Memory)
1: Address is 8400h—87FFh (Data and Program Memory)