Datasheet

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SBAS323G − JUNE 2004 − REVISED OCTOBER 2007
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Timer 0 MSB (TH0)
7 6 5 4 3 2 1 0 Reset Value
SFR 8Ch TH0.7 TH0.6 TH0.5 TH0.4 TH0.3 TH0.2 TH0.1 TH0.0 00h
TH0.7−0 Timer 0 MSB. This register contains the most significant byte of Timer 0.
bits 7−0
Timer 1 MSB (TH1)
7 6 5 4 3 2 1 0 Reset Value
SFR 8Dh TH1.7 TH1.6 TH1.5 TH1.4 TH1.3 TH1.2 TH1.1 TH1.0 00h
TH1.7−0 Timer 1 MSB. This register contains the most significant byte of Timer 1.
bits 7−0
Clock Control (CKCON)
7 6 5 4 3 2 1 0 Reset Value
SFR 8Eh 0 0 T2M T1M T0M MD2 MD1 MD0 01h
T2M Timer 2 Clock Select. This bit controls the division of the system clock that drives Timer 2. This bit has no effect when
bit 5 the timer is in baud rate generator or clock output modes. Clearing this bit to 0 maintains 8051 compatibility. This bit
has no effect on instruction cycle timing.
0: Timer 2 uses a divide by 12 of the crystal frequency.
1: Timer 2 uses a divide by 4 of the crystal frequency.
T1M Timer 1 Clock Select. This bit controls the division of the system clock that drives Timer 1. Clearing this bit to 0
bit 4 maintains 8051 compatibility. This bit has no effect on instruction cycle timing.
0: Timer 1 uses a divide by 12 of the crystal frequency.
1: Timer 1 uses a divide by 4 of the crystal frequency.
T0M Timer 0 Clock Select. This bit controls the division of the system clock that drives Timer 0. Clearing this bit to 0
bit 3 maintains 8051 compatibility. This bit has no effect on instruction cycle timing.
0: Timer 0 uses a divide by 12 of the crystal frequency.
1: Timer 0 uses a divide by 4 of the crystal frequency.
MD2, MD1, MD0 Stretch MOVX Select 2−0. These bits select the time by which external MOVX cycles are to be stretched. This
bits 2−0 allows slower memory or peripherals to be accessed without using ports or manual software intervention. The
width of the RD
or WR strobe will be stretched by the specified interval, which will be transparent to the software
except for the increased time to execute the MOVX instruction. All internal MOVX instructions on devices
containing MOVX SRAM are performed at the 2 instruction cycle rate.
MD2 MD1 MD0
STRETCH
VALUE
MOVX DURATION
RD or WR STROBE
WIDTH (SYS CLKs)
RD or WR STROBE
WIDTH (ms) at 12MHz
0 0 0 0 2 Instruction Cycles 2 0.167
0 0 1 1 3 Instruction Cycles (default) 4 0.333
0 1 0 2 4 Instruction Cycles 8 0.667
0 1 1 3 5 Instruction Cycles 12 1.000
1 0 0 4 6 Instruction Cycles 16 1.333
1 0 1 5 7 Instruction Cycles 20 1.667
1 1 0 6 8 Instruction Cycles 24 2.000
1 1 1 7 9 Instruction Cycles 28 2.333