Datasheet

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SBAS323G − JUNE 2004 − REVISED OCTOBER 2007
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40
INTERRUPTS
The MSC1211/12/13/14 use a three-priority interrupt
system. As shown in Table 8, each interrupt source has an
independent priority bit, flag, interrupt vector, and enable
(except that nine interrupts share the Auxiliary Interrupt
(AI) at the highest priority). In addition, interrupts can be
globally enabled or disabled. The interrupt structure is
compatible with the original 8051 family. All of the standard
interrupts are available.
Table 8. Interrupt Summary
INTERRUPT
PRIORITY
INTERRUPT/EVENT
ADDR NUM
PRIORITY FLAG ENABLE
PRIORITY
CONTROL
DV
DD
Low Voltage/HW Break-
point
33h 6 High EDLVB (AIE.0 or AIPOL.0)
(1)(2)
EBP (BPCON.7)
(1)
EDLVB (AIE.0)
(1)
EBP (BPCON.0)
(1)
N/A
AV
DD
Low Voltage 33h 6 0 EALV (AIE.1 or AIPOL.1)
(1)(2)
EALV (AIE.1)
(1)
N/A
SPI Receive / I
2
C
(3)
33h 6 0 ESPIR/EI2C (AIE.2 or AIPOL.2)
(1)(2)
ESPIR/EI2C (AIE.2)
(1)
N/A
SPI Transmit 33h 6 0 ESPIT (AIE.3 or AIPOL.3)
(1)(2)
ESPIT (AIE.3)
(1)
N/A
Milliseconds Timer 33h 6 0 EMSEC (AIE.4 or AIPOL.4)
(1)(2)
EMSEC (AIE.4)
(1)
N/A
ADC 33h 6 0 EADC (AIE.5 or AIPOL.5)
(1)(2)
EADC (AIE.5)
(1)
N/A
Summation Register 33h 6 0 ESUM (AIE.6 or AIPOL.6)
(1)(2)
ESUM (AIE.6)
(1)
N/A
Seconds Timer 33h 6 0 ESEC (AIE.7 or AIPOL.7)
(1)(2)
ESEC (AIE.7)
(1)
N/A
External Interrupt 0 03h 0 1 IE0 (TCON.1)
(4)
EX0 (IE.0)
(6)
PX0 (IP.0)
Timer 0 Overflow 0Bh 1 2 TF0 (TCON.5)
(5)
ET1 (IE.1)
(6)
PT0 (IP.1)
External Interrupt 1 13h 2 3 IE1 (TCON.3)
(4)
EX1 (IE.2)
(6)
PX1 (IP.2)
Timer 1 Overflow 0Bh 3 4 TF1 (TCON.7)
(5)
ET1 (IE.3)
(6)
PT1 (IP.3)
Serial Port 0 23h 4 5 RI_0 (SCON0.0)
TI_0 (SCON0.1)
ES0 (IE.4)
(6)
PS0 (IP.4)
Timer 2 Overflow 2Bh 5 6 TF2 (T2CON.7) ET2 (IE.5)
(6)
PT2 (IP.5)
Serial Port 1 3Bh 7 7 RI_1 (SCON1.0)
TI_1 (SCON1.1)
ES1 (IE.6)
(6)
PS1 (IP.6)
External Interrupt 2 43h 8 8 IE2 (EXIF.4)
(4)
EX2 (EIE.0)
(6)
PX2 (EIP.0)
External Interrupt 3 4Bh 9 9 IE3 (EXIF.5)
(4)
EX3 (EIE.1)
(6)
PX3 (EIP.1)
External Interrupt 4 53h 10 10 IE4 (EXIF.6)
(4)
EX4 (EIE.2)
(6)
PX4 (EIP.2)
External Interrupt 5 5Bh 11 11 IE5 (EXIF.7)
(4)
EX5 (EIE.3)
(6)
PX5 (EIP.3)
Watchdog 63h 12 12
Low
WDTI (EICON.3) EWDI (EIE.4)
(6)
PWDI (EIP.4)
(1)
These interrupts set the AI flag (EICON.4) and are enabled by EAI (EICON.5).
(2)
For AIPOL.RDSEL = 1, reading AIPOL register gives current value of Auxiliary interrupts before masking. Reading AIE register gives value of
AIE register contents.
For AIPOL.RDSEL = 0, Reading AIPOL register gives value of AIE register contents. Reading AIE register gives current value of Auxiliary
interrupts before masking.
(3)
I
2
C is only available on the MSC1211 and MSC1213.
(4)
If edge-triggered, cleared automatically by hardware on interrupt service routine vector. For EX0 or EX1, if level-triggered, the flag follows the
state of the pin.
(5)
Cleared automatically by hardware when interrupt vector occurs.
(6)
Globally enabled by EA (IE.7).