Datasheet

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SBAS203J − MARCH 2002 − REVISED JANUARY 2008
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83
Hardware Version Register (HDWVER)
7 6 5 4 3 2 1 0 Reset Value
SFR EBh
Flash Memory Control (FMCON)
7 6 5 4 3 2 1 0 Reset Value
SFR EEh 0 PGERA 0 FRCM 0 BUSY 1 0 02h
PGERA Page Erase.
bit 6 0 = MOVX to Flash will perform a byte write operation
1 = MOVX to Flash will perform a page erase operation
FRCM Frequency Control Mode.
bit 4 0 = Bypass (default)
1 = Use Delay Line. Saves power when reading Flash (recommended)
BUSY Write/Erase BUSY Signal.
bit 2 0 = Idle or Available
1 = Busy
Flash Memory Timing Control Register (FTCON)
7 6 5 4 3 2 1 0 Reset Value
SFR EFh FER3 FER2 FER1 FER0 FWR3 FWR2 FWR1 FWR0 A5h
Refer to Flash Timing Characteristics.
FER3−0 Set Erase. Flash Erase Time = (1 + FER) • (MSEC + 1) • t
CLK
.
bits 7−4 A minimum of 10ms is needed for industrial temperature range.
A minimum of 4ms is needed for commercial temperature range.
FWR3−0 Set Write. Flash Write Time = (1 + FWR) • (USEC + 1) • 5 • t
CLK
.
bits 3−0 Write time should be 30−40µs.
B Register (B)
7 6 5 4 3 2 1 0 Reset Value
SFR F0h B.7 B.6 B.5 B.4 B.3 B.2 B.1 B.0 00h
B.7−0 B Register. This register serves as a second accumulator for certain arithmetic operations.
bits 7−0