Datasheet

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SBAS203J − MARCH 2002 − REVISED JANUARY 2008
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80
Summation Register 0 (SUMR0)
7 6 5 4 3 2 1 0 Reset Value
SFR E2h LSB 00h
SUMR0 Summation Register 0. This is the least significant byte of the 32-bit summation register or bits 0 to 7.
bits 7−0 Write: Will cause values in SUMR3−0 to be added to the summation register.
Read: Will clear the Summation Count Interrupt. AI in EICON (SFR D8h) must also be cleared.
Summation Register 1 (SUMR1)
7 6 5 4 3 2 1 0 Reset Value
SFR E3h 00h
SUMR1 Summation Register 1. These are bits 8−15 of the 32-bit summation register.
bits 7−0
Summation Register 2 (SUMR2)
7 6 5 4 3 2 1 0 Reset Value
SFR E4h 00h
SUMR2 Summation Register 2. These are bits 16−23 of the 32-bit summation register.
bits 7−0
Summation Register 3 (SUMR3)
7 6 5 4 3 2 1 0 Reset Value
SFR E5h MSB 00h
SUMR3 Summation Register 3. This is the most significant byte of the 32-bit summation register or bits 24−31.
bits 7−0
Offset DAC Register (ODAC)
7 6 5 4 3 2 1 0 Reset Value
SFR E6h 00h
ODAC Offset DAC Register. This register will shift the input by up to half of the ADC full-scale input range. The offset DAC
bits 7−0 value is summed with the ADC input prior to conversion. Writing 00h or 80h to ODAC turns off the offset DAC.
bit 7 Offset DAC Sign bit.
0 = Positive
1 = Negative
bit 6−0
Offset +
*V
REF
2 @ PGA
@
ǒ
ODAC
ƪ
6:0
ƫ
127
Ǔ
@
(
* 1
)
bit7
NOTE: ODAC cannot be used to offset the input so that the buffer can be used for AGND signals. Offset DAC should be
cleared before offset calibration, since the offset DAC output is applied directly to the ADC input.