Datasheet

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SBAS203J − MARCH 2002 − REVISED JANUARY 2008
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79
Accumulator (A or ACC)
7 6 5 4 3 2 1 0 Reset Value
SFR E0h ACC.7 ACC.6 ACC.5 ACC.4 ACC.3 ACC.2 ACC.1 ACC.0 00h
ACC.7−0 Accumulator. This register serves as the accumulator for arithmetic and logic operations.
bits 7−0
Summation/Shifter Control (SSCON)
7 6 5 4 3 2 1 0 Reset Value
SFR E1h SSCON1 SSCON0 SCNT2 SCNT1 SCNT0 SHF2 SHF1 SHF0 00h
The Summation register is powered down when the ADC is powered down. If all zeroes are written to this register the 32-bit
SUMR3−0 registers will be cleared. The Summation registers will do sign extend if Bipolar is selected in ADCON1.
SSCON1−0 Summation/Shift Count.
bits 7−6
SOURCE SSCON1 SSCON0 MODE
CPU 0 0 Values written to the SUM registers are accumulated when the SUMR0 value is written (sum/shift ignored)
ADC 0 1 Summation register Enabled. Source is ADC, summation count is working.
CPU 1 0 Shift Enabled. Summation register is shifted by SHF Count bits. It takes four system clocks to execute.
ADC 1 1 Accumulate and Shift Enable. Values are accumulated for SUM Count times and then shifted by SHF Count.
SCNT2−0 Summation Count. When the summation is complete an interrupt will be generated unless masked. Reading the
bits 5−3 SUMR0 register clears the interrupt.
SCNT2 SCNT1 SCNT0 SUMMATION COUNT
0 0 0 2
0 0 1 4
0 1 0 8
0 1 1 16
1 0 0 32
1 0 1 64
1 1 0 128
1 1 1 256
SHF2−0 Shift Count.
bits 2−0
SHF2 SHF1 SHF0 SHIFT DIVIDE
0 0 0 1 2
0 0 1 2 4
0 1 0 3 8
0 1 1 4 16
1 0 0 5 32
1 0 1 6 64
1 1 0 7 128
1 1 1 8 256