Datasheet

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SBAS203J − MARCH 2002 − REVISED JANUARY 2008
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55
Tone Low (TONELOW)/PWM Low (PWMLOW)
7 6 5 4 3 2 1 0 Reset Value
SFR A2h
TDIV7
PWM7
TDIV6
PWM6
TDIV5
PWM5
TDIV4
PWM4
TDIV3
PWM3
TDIV2
PWM2
TDIV1
PWM1
TDIV0
PWM0
00h
TDIV7−0 Tone Divisor. The low order bits that define the half-time period. For staircase mode the output is high impedance
bits 7−0 for the last 1/4 of this period.
PWMLOW Pulse Width Modulator Low Bits. These 8 bits are the least significant 8 bits of the PWM register.
bits 7−0
Tone High (TONEHI)/PWM High (PWMHI)
7 6 5 4 3 2 1 0 Reset Value
SFR A3h
TDIV15
PWM15
TDIV14
PWM14
TDIV13
PWM13
TDIV12
PWM12
TDIV11
PWM11
TDIV10
PWM10
TDIV9
PWM9
TDIV8
PWM8
00h
TDIV15−8 Tone Divisor. The high order bits that define the half time period. For staircase mode the output is high impedance
bits 7−0 for the last 1/4 of this period.
PWMHI Pulse Width Modulator High Bits. These 8 bits are the high order bits of the PWM register.
bits 7−0
Pending Auxiliary Interrupt (PAI)
7 6 5 4 3 2 1 0 Reset Value
SFR A5h — — — — PAI3 PAI2 PAI1 PAI0 00h
PAI Pending Auxiliary Interrupt Register. The results of this register can be used as an index to vector to the
bits 3−0 appropriate interrupt routine. All of these interrupts vector through address 0033h.
PAI3 PAI2 PAI1 PAI0 AUXILIARY INTERRUPT STATUS
0 0 0 0 No Pending Auxiliary IRQ
0 0 0 1 Digital Low Voltage IRQ Pending
0 0 1 0 Analog Low Voltage IRQ Pending
0 0 1 1 SPI Receive IRQ Pending.
0 1 0 0 SPI Transmit IRQ Pending.
0 1 0 1 One Millisecond System Timer IRQ Pending.
0 1 1 0 Analog-to-Digital Conversion IRQ Pending.
0 1 1 1 Accumulator IRQ Pending.
1 0 0 0 One Second System Timer IRQ Pending.