Datasheet

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SBAS203J − MARCH 2002 − REVISED JANUARY 2008
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54
SPI Transmit Control Register (SPITCON)
7 6 5 4 3 2 1 0 Reset Value
SFR 9Dh CLK_EN DRV_DLY DRV_EN 00h
CLK_EN SCK Driver Enable.
bit 5 0: Disable SCK Driver (Master Mode)
1: Enable SCK Driver (Master Mode)
DRV_DLY Drive Delay. (Refer to DRV_EN bit)
bit 4 0: Drive output immediately
1: Drive output after current byte transfer
DRV_EN Drive Enable.
bit 3
DRV_DLY DRV_EN MOSI or MISO OUTPUT CONTROL
0 0 Tristate immediately
0 1 Drive immediately
1 0 Tristate after the current byte transfer
1 1 Drive after the current byte transfer
Port 2 (P2)
7 6 5 4 3 2 1 0 Reset Value
SFR A0h FFh
P2 Port 2. This port functions as an address bus during external memory access, and as a general-purpose I/O port.
bits 7−0 During external memory cycles, this port will contain the MSB of the address. Whether Port 2 is used as
general-purpose I/O or for external memory access is determined by the Flash Configuration Register (HCR1.0).
PWM Control (PWMCON)
7 6 5 4 3 2 1 0 Reset Value
SFR A1h — — PPOL PWMSEL SPDSEL TPCNTL2 TPCNTL1 TPCNTL0 00h
PPOL Period Polarity. Specifies the starting level of the PWM pulse.
bit 5 0: ON Period. PWM Duty register programs the ON period.
1: OFF Period. PWM Duty register programs the OFF period.
PWMSEL PWM Register Select. Select which 16-bit register is accessed by PWMLOW/PWMHIGH.
bit 4 0: Period (must be 0 for TONE mode)
1: Duty
SPDSEL Speed Select.
bit 3 0: 1MHz (the USEC Clock)
1: SYSCLK
TPCNTL Tone Generator/Pulse Width Modulation Control.
bits 2−0
TPCNTL.2 TPCNTL.1 TPCNTL.0 MODE
0 0 0 Disable (default)
0 0 1 PWM
0 1 1 TONE—Square
1 1 1 TONE—Staircase