Datasheet

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SBAS203J − MARCH 2002 − REVISED JANUARY 2008
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36
INTERRUPTS
The MSC1210 uses a three-priority interrupt system. As
shown in Table 7, each interrupt source has an
independent priority bit, flag, interrupt vector, and enable
(except that nine interrupts share the Auxiliary Interrupt
[AI] at the highest priority). In addition, interrupts can be
globally enabled or disabled. The interrupt structure is
compatible with the original 8051 family. All of the standard
interrupts are available.
HARDWARE CONFIGURATION MEMORY
The 128 configuration bytes can only be written during the
program mode. The bytes are accessed through SFR
registers CADDR (SFR 93h) and CDATA (SFR 94h). Two
of the configuration bytes control Flash partitioning and
system control. If the security bit is set, these bits can not
be changed except with a Mass Erase command that
erases all of the Flash Memory including the 128
configuration bytes.
Table 7. Interrupt Summary
INTERRUPT
PRIORITY
INTERRUPT/EVENT
ADDR NUM
PRIORITY FLAG ENABLE
PRIORITY
CONTROL
DV
DD
Low Voltage/HW Breakpoint 33h 6 HIGH EDLVB (AIE.0)
(1)
EBP (BPCON.0)
(1)
EDLVB (AIE.0)
(1)
EBP (BPCON.0)
(1)
N/A
AV
DD
Low Voltage 33h 6 0 EALV (AIE.1)
(1)
EALV (AIE.1)
(1)
N/A
SPI Receive 33h 6 0 ESPIR (AIE.2)
(1)
ESPIR (AIE.2)
(1)
N/A
SPI Transmit 33h 6 0 ESPIT (AIE.3)
(1)
ESPIT (AIE.3)
(1)
N/A
Milliseconds Timer 33h 6 0 EMSEC (AIE.4)
(1)
EMSEC (AIE.4)
(1)
N/A
ADC 33h 6 0 EADC (AIE.5)
(1)
EADC (AIE.5)
(1)
N/A
Summation Register 33h 6 0 ESUM (AIE.6)
(1)
ESUM (AIE.6)
(1)
N/A
Seconds Timer 33h 6 0 ESEC (AIE.7)
(1)
ESEC (AIE.7)
(1)
N/A
External Interrupt 0 03h 0 1 IE0 (TCON.1)
(2)
EX0 (IE.0)
(4)
PX0 (IP.0)
Timer 0 Overflow 0Bh 1 2 TF0 (TCON.5)
(3)
ET1 (IE.1)
(4)
PT0 (IP.1)
External Interrupt 1 13h 2 3 IE1 (TCON.3)
(2)
EX1 (IE.2)
(4)
PX1 (IP.2)
Timer 1 Overflow 0Bh 3 4 TF1 (TCON.7)
(3)
ET1 (IE.3)
(4)
PT1 (IP.3)
Serial Port 0 23h 4 5 RI_0 (SCON0.0)
TI_0 (SCON0.1)
ES0 (IE.4)
(4)
PS0 (IP.4)
Timer 2 Overflow 2Bh 5 6 TF2 (T2CON.7) ET2 (IE.5)
(4)
PT2 (IP.5)
Serial Port 1 3Bh 7 7 RI_1 (SCON1.0)
TI_1 (SCON1.1)
ES1 (IE.6)
(4)
PS1 (IP.6)
External Interrupt 2 43h 8 8 IE2 (EXIF.4) EX2 (EIE.0)
(4)
PX2 (EIP.0)
External Interrupt 3 4Bh 9 9 IE3 (EXIF.5) EX3 (EIE.1)
(4)
PX3 (EIP.1)
External Interrupt 4 53h 10 10 IE4 (EXIF.6) EX4 (EIE.2)
(4)
PX4 (EIP.2)
External Interrupt 5 5Bh 11 11 IE5 (EXIF.7) EX5 (EIE.3)
(4)
PX5 (EIP.3)
Watchdog 63h 12 12
LOW
WDTI (EICON.3) EWDI (EIE.4)
(4)
PWDI (EIP.4)
(1)
These interrupts set the AI flag (EICON.4) and are enabled by EAI (EICON.5).
(2)
If edge-triggered, cleared automatically by hardware when the service routine is vectored to. If level-triggered, the flag follows the state of the
pin.
(3)
Cleared automatically by hardware when interrupt vector occurs.
(4)
Globally enabled by EA (IE.7).