Datasheet

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SBAS203J − MARCH 2002 − REVISED JANUARY 2008
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31
CONFIGURATION MEMORY
The MSC1210 Configuration Memory consists of 128 bytes.
In UAM, all Configuration Memory is readable using the
faddr_data_read Boot ROM routine, and the CADDR and
CDATA registers. In UAM, however, none of the
Configuration Memory is writable.
In serial or parallel programming mode, all Configuration
Memory is readable. Most locations are also writable, except
for addresses 8070h through 8079h, which are read-only.
The two hardware configuration registers reside in
configuration memory at 807Eh (HCR1) and 807Fh (HCR0).
Figure 19 shows the configuration memory mapping for
programming mode and UAM. Note that reading/writing
configuration memory in Flash Programming mode (FPM)
requires 16-bit addressing, whereas reading configuration
memory in User Application mode (UAM) requires only
8-bit addressing.
Read−Only in Both
FPM and UAM
00h UAM Address
HCR0
HCR1
7Fh
79h
70h
7Fh0807Fh
0807Eh
08079h
08070h
08000h
Flash
Programming
Mode
User
Application
Mode
(Read−Only)
NOTE: All Configuration Memory is R/W in programming mode, except
addresses 8070h−8079h, which are read−only. All Configuration
Memory is read−only in UAM.
Figure 19. Configuration Memory Map
REGISTER MAP
The Register Map is illustrated in Figure 20. It is entirely
separate from the Program and Data Memory areas
mentioned before. A separate class of instructions is used
to access the registers. There are 256 potential register
locations. In practice, the MSC1210 has 256 bytes of
Scratchpad RAM and up to 128 SFRs. This is possible,
since the upper 128 Scratchpad RAM locations can only
be accessed indirectly. Thus, a direct reference to one of
the upper 128 locations must be an SFR access. Direct
RAM is reached at locations 0 to 7Fh (0 to 127).
FFh 255
128
FFh
80h
80h
7Fh
0000h
Indirect
RAM
Direct
RAM
Scratchpad
RAM
SFR Registers
Direct
Special
Function
Registers
Figure 20. Register Map
SFRs are accessed directly between 80h and FFh (128 to
255). The RAM locations between 128 and 255 can be
reached through an indirect reference to those locations.
Scratchpad RAM is available for general-purpose data
storage. It is commonly used in place of off-chip RAM
when the total data contents are small. When off-chip RAM
is needed, the Scratchpad area will still provide the fastest
general-purpose access. Within the 256 bytes of RAM,
there are several special-purpose areas.
Bit Addressable Locations
In addition to direct register access, some individual bits
are also accessible. These are individually addressable
bits in both the RAM and SFR area. In the Scratchpad
RAM area, registers 20h to 2Fh are bit addressable. This
provides 128 (16 × 8) individual bits available to software.
A bit access is distinguished from a full-register access by
the type of instruction. In the SFR area, any register
location ending in a 0 or 8 is bit addressable. Figure 21
shows details of the on-chip RAM addressing including the
locations of individual RAM bits.
Working Registers
As part of the lower 128 bytes of RAM, there are four banks
of Working Registers, as shown in Figure 21. The Working
Registers are general-purpose RAM locations that can be
addressed in a special way. They are designated R0