Datasheet

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SBAS203J − MARCH 2002 − REVISED JANUARY 2008
www.ti.com
3
ELECTRICAL CHARACTERISTICS: AV
DD
= 5V
All specifications from T
MIN
to T
MAX
, DV
DD
= +2.7V to 5.25V, f
MOD
= 15.625kHz, PGA = 1, Buffer ON, f
DATA
= 10Hz, Bipolar, and V
REF
≡ (REF IN+) − (REF IN−) = +2.5V,
unless otherwise noted.
MSC1210Yx
PARAMETER CONDITIONS MIN TYP MAX UNITS
Analog Input (AIN0-AIN7, AINCOM)
Analog Input Range
Buffer OFF AGND − 0.1 AV
DD
+ 0.1 V
Analog Input Range
Buffer ON AGND + 50mV AV
DD
− 1.5 V
Full-Scale Input Voltage Range (In+) − (In−) ±V
REF
/PGA V
Differential Input Impedance Buffer OFF 7/PGA
(5)
MΩ
Input Current Buffer ON 0.5 nA
Fast Settling Filter −3dB 0.469 • f
DATA
Bandwidth
Sinc
2
Filter −3dB 0.318 • f
DATA
Bandwidth
Sinc
3
Filter −3dB 0.262 • f
DATA
Programmable Gain Amplifier User-Selectable Gain Range 1 128
Input Capacitance Buffer On 9 pF
Input Leakage Current Multiplexer channel OFF, T = +25°C 0.5 pA
Burnout Current Sources Buffer On 2 µA
Offset DAC
Offset DAC Range ±V
REF
/(2•PGA) V
Offset DAC Monotonicity 8 Bits
Offset DAC Gain Error ±1.5 % of Range
Offset DAC Gain Error Drift 1 ppm/°C
System Performance
Resolution 24 Bits
ENOB See Typical Characteristics
Output Noise See Typical Characteristics
No Missing Codes Sinc
3
Filter, Decimation > 360 24 Bits
Integral Nonlinearity End Point Fit, Differential Input ±0.0015 % of FSR
Offset Error After Calibration 7.5 ppm of FS
Offset Drift
(1)
Before Calibration 0.1 ppm of FS/°C
Gain Error
(2)
After Calibration 0.002 %
Gain Error Drift
(1)
Before Calibration 0.5 ppm/°C
System Gain Calibration Range 80 120 % of FS
System Offset Calibration Range −50 50 % of FS
At DC 100 115 dB
ADC Common-Mode Rejection
f
CM
= 60Hz
,
f
DATA
= 10Hz 130 dB
ADC Common-Mode Rejection
f
CM
= 50Hz
,
f
DATA
= 50Hz 120 dB
f
CM
= 60Hz
,
f
DATA
= 60Hz 120 dB
Normal-Mode Rejection
f
SIG
= 50Hz
,
f
DATA
= 50Hz 100 dB
Normal-Mode Rejection
f
SIG
= 60Hz
,
f
DATA
= 60Hz 100 dB
Power-Supply Rejection At DC, dB = −20log(∆V
OUT
/∆V
DD
)
(3)
80 88 dB
(1)
Calibration can minimize these errors.
(2)
The self-gain calibration cannot have a REF IN+ of more than AV
DD
−1.5V with Buffer ON. To calibrate gain, turn Buffer OFF.
(3)
∆V
OUT
is change in digital result.
(4)
9pF switched capacitor at f
SAMP
clock frequency (see Figure 14).
(5)
The input impedance for PGA = 128 is the same as that for PGA = 64 (that is, 7MΩ/64).