Datasheet
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SBAS203J − MARCH 2002 − REVISED JANUARY 2008
www.ti.com
28
IDLE MODE
Idle mode is entered by setting the IDLE bit in the Power
Control register (PCON, 087h). In Idle mode, the CPU,
Timer0, Timer1, and USARTs are stopped, but all other
peripherals and digital pins remain active. The device can
be returned to active mode via an active internal or external
interrupt. This mode is typically used for reducing power
consumption between ADC samples.
By configuring the device prior to entering Idle mode,
further power reductions can be achieved (while in Idle
mode). These reductions include powering down
peripherals not in use in the PDCON register (0F1h).
STOP MODE
Stop mode is entered by setting the STOP bit in the Power
Control register (PCON, 087h). In Stop mode, all internal
clocks are halted. This mode has the lowest power
consumption. The device can be returned to active mode
only via an external or power-on reset.
By configuring the device prior to entering Stop mode,
further power reductions can be achieved (while in Stop
mode). These power reductions include halting the
external clock into the device, configuring all digital I/O
pins as open drain with low output drive, disabling the ADC
buffer, disabling the internal V
REF
, and setting PDCON to
0FFh to power down all peripherals.
In Stop mode, if the brownout reset is enabled, there is
approximately 25µA of draw from the power supply. To
achieve zero current (≈ 100nA) in Stop mode, disable the
brownout reset via HCR1.
In Stop mode, all digital pins retain their values.
POWER CONSUMPTION CONSIDERATIONS
The following suggestions will reduce current
consumption:
1. Use the lowest supply voltage that will work in the
application for both AV
DD
and DV
DD
.
2. Use the lowest clock frequency that will work in the
application.
3. Use Idle mode and the system clock divider whenever
possible. Note that the system clock divider also affects
the ADC clock.
4. Avoid using 8051-compatible I/O mode on the I/O ports.
The internal pull-up resistors will draw current when the
outputs are low.
5. Use the delay line for Flash Memory control by setting the
FRCM bit in the FMCON register (SFR EEh)
6. Power down peripherals when they are not needed.
Refer to SFR PDCON, LVDCON, and ADCON0.
MEMORY MAP
The MSC1210 contains on-chip SFR, Flash Memory,
Scratchpad SRAM Memory, Boot ROM, and SRAM. THe
SFR registers are primarily used for control and status.
The standard 8051 features and additional peripheral
features of the MSC1210 are controlled through the SFR.
Reading from an undefined SFR and writing to undefined
SFR registers is not recommended, and will have
indeterminate effects.
Flash Memory is used for both Program Memory and Data
Memory. The user has the ability to select the partition size
of Program and Data Memories. The partition size is set
through hardware configuration bits, which are
programmed through either the parallel or serial
programming methods. Both Program and Data Flash
Memories are erasable and writable (programmable) in
User Application mode (UAM). However, program
execution can only occur from Program Memory.
As an added precaution, a lock feature can be activated
through the hardware configuration bits, which disables
erase and writes to 4kB of Program Flash Memory or the
entire Program Flash Memory in UAM.
The MSC1210 includes 1kB of SRAM on-chip. SRAM starts
at address 0 and is accessed through the MOVX instruction.
This SRAM can also be located to start at 8400h and can be
accessed as both Program and Data Memory.