Datasheet

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SBAS203J − MARCH 2002 − REVISED JANUARY 2008
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22
Furthermore, improvements were made to peripheral
features that off-load processing from the core, and the
user, to further improve efficiency. For instance, 32-bit
accumulation can be done through the summation register
to significantly reduce the processing overhead for the
multiple byte data from the ADC or other sources. This
allows for 32-bit addition and shifting to be accomplished
in a few instruction cycles, compared to hundreds of
instruction cycles through a software implementation.
Family Device Compatibility
The hardware functionality and pin configuration across the
MSC1210 family are fully compatible. To the user the only
difference between family members is the memory
configuration. This makes migration between family
members simple. Code written for the MSC1210Y2 can be
executed directly on an MSC1210Y3, MSC1210Y4, or
MSC1210Y5. This gives the user the ability to add or subtract
software functions and to freely migrate between family
members. Thus, the MSC1210 can become a standard
device used across several application platforms.
Family Development Tools
The MSC1210 is fully compatible with the standard 8051
instruction set. This means that the user can develop
software for the MSC1210 with their existing 8051
development tools. Additionally, a complete, integrated
development environment is provided with each demo
board, and third-party developers also provide support.
Power Down Modes
The MSC1210 can power down several of the on-chip
peripherals and put the CPU into IDLE. For more information,
see the Idle Mode and Stop Mode sections.
USEC
FB
MSECH
HMSEC
FE
MSINT
FA
ACLK
F6
divide
by 64
Internal
V
REF
MSECL
FD
FC
ms
µ
s
100ms
Flash Write
Timing
Flash Erase
Timing
WDTCON
SECINT
F9
FF
FTCON
[3:0]
FTCON
[7:4]
EF
EF
seconds
interrupt
watchdog
milliseconds
interrupt
ADC Output Rate
ADCON3 ADCON2
DF DE
Decimation Ratio
SYS Clock
Oscillator
PWMHI PWMLOW
A3 A2
PWM Clock
SPICON
9A
SCK
t
CLK
(30
µ
sto40
µ
s)
(5ms to 11ms)
STOP
PDCON.0
PDCON.4
PDCON.1
PDCON.2
PDCON.3
IDLE
CPU Clock
Timers 0/1/2
ADC Power Down
USART0/1
ADCON0
DC
f
SAMP
f
DATA
f
MOD
(see Figure 14)
Figure 11. MSC1210 Timing Chain and Clock Control