Datasheet

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SBAS203J − MARCH 2002 − REVISED JANUARY 2008
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21
ENHANCED 8051 CORE
All instructions in the MSC1210 family perform exactly the
same functions as they would in a standard 8051. The
effect on bits, flags, and registers is the same. However,
the timing is different. The MSC1210 family utilizes an
efficient 8051 core which results in an improved instruction
execution speed of between 1.5 and 3 times faster than the
original core for the same external clock speed (4 clock
cycles per instruction versus 12 clock cycles per
instruction, as shown in Figure 9). The internal system
clock is equal to the external oscillator frequency. This
translates into an effective throughput improvement of
more than 2.5 times, using the same code and same
external clock speed.
Therefore, a device frequency of 33MHz for the
MSC1210Yx actually performs at an equivalent execution
speed of 82.5MHz compared to the standard 8051 core.
This allows the user to run the device at slower external
clock speeds which reduces system noise and power
consumption, but provides greater throughput. This
performance difference can be seen in Figure 10. The
timing of software loops will be faster with the MSC1210.
However, the timer/counter operation of the MSC1210
may be maintained at 12 clocks per increment or optionally
run at 4 clocks per increment.
The MSC1210 also provides dual data pointers (DPTRs)
to speed block Data Memory moves.
Additionally, it can stretch the number of memory cycles to
access external Data Memory from between two and nine
instruction cycles in order to accommodate different
speeds of memory or devices, as shown in Table 1. The
MSC1210 provides an external memory interface with a
16-bit address bus (P0 and P2). The 16-bit address bus
makes it necessary to multiplex the low address byte
through the P0 port. To enhance P0 and P2 for high-speed
memory access, hardware configuration control is
provided to configure the ports for external
memory/peripheral interface or general-purpose I/O.
ALE
PSEN
AD0−AD7
PORT 2
ALE
PSEN
AD0−AD7
PORT 2
CLK
Standard 8051 Timing MSC121 Timing
Single−Byte, Single−Cycle
Instruction
Instruction
12 Cycles
4 Cycles
0
Single−Byte, Single−Cycle
Figure 10. Comparison of MSC1210 Timing to
Standard 8051 Timing
Table 1. Memory Cycle Stretching. Stretching of
MOVX timing as defined by MD2, MD1, and MD0
bits in CKCON register (address 8Eh).
CKCON
(8Eh)
MD2:MD0
INSTRUCTION
CYCLES
(for MOVX)
RD or WR
STROBE WIDTH
(SYS CLKs)
RD or WR
STROBE WIDTH
(ms) AT 12MHz
000 2 2 0.167
001 3 (default) 4 0.333
010 4 8 0.667
011 5 12 1.000
100 6 16 1.333
101 7 20 1.667
110 8 24 2.000
111 9 28 2.333
CLK
instr_cycle
cpu_cycle
C1 C2 C3 C4 C1 C2 C3 C4 C1
n+1 n+2
Figure 9. Instruction Timing Cycle