Datasheet

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SBAS203J − MARCH 2002 − REVISED JANUARY 2008
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10
t
WHLH
t
AVLL
t
LLWL
t
WHQX
t
LLAX
t
AVWL
t
WLWH
t
DW
t
QVWX
ALE
WR
PSEN
PORT 0
PORT 2
from RI or DPL
DATA OUT from PCL INSTR IN
P2.0−P2.7or A8−A15 from DPH A8−A15 from PCH
A0−A7
A0−A7
Figure 3. External Data Memory Write Cycle
t
r
t
HIGH
V
IH1
V
IH1
0.8V 0.8V
V
IH1
V
IH1
0.8V 0.8V
t
LOW
t
t
f
CLK
Figure 4. External Clock Drive CLK