MSC1210 SBAS203J − MARCH 2002 − REVISED JANUARY 2008 Precision Analog-to-Digital Converter (ADC) with 8051 Microcontroller and Flash Memory FEATURES ANALOG FEATURES D 24 Bits No Missing Codes D 22 Bits Effective Resolution at 10Hz D D D D D D D D D D − Low Noise: 75nV PGA From 1 to 128 Precision On-Chip Voltage Reference 8 Differential/Single-Ended Channels On-Chip Offset/Gain Calibration Offset Drift: 0.1ppm/°C Gain Drift: 0.
"# $%$& www.ti.com SBAS203J − MARCH 2002 − REVISED JANUARY 2008 PACKAGE/ORDERING INFORMATION(1) PRODUCT FLASH MEMORY PACKAGE MARKING MSC1210Y2 4k MSC1210Y2 MSC1210Y3 8k MSC1210Y3 MSC1210Y4 16k MSC1210Y4 MSC1210Y5 32k MSC1210Y5 (1) For the most current package and ordering information, see the Package Option Addendum at the end of this datasheet, or refer to our web site at www.ti.com. This integrated circuit can be damaged by ESD.
"# $%$& www.ti.com SBAS203J − MARCH 2002 − REVISED JANUARY 2008 ELECTRICAL CHARACTERISTICS: AVDD = 5V All specifications from TMIN to TMAX, DVDD = +2.7V to 5.25V, fMOD = 15.625kHz, PGA = 1, Buffer ON, fDATA = 10Hz, Bipolar, and VREF ≡ (REF IN+) − (REF IN−) = +2.5V, unless otherwise noted. MSC1210Yx PARAMETER CONDITIONS MIN TYP MAX UNITS AVDD + 0.1 V AVDD − 1.5 V Analog Input (AIN0-AIN7, AINCOM) Analog Input Range Buffer OFF AGND − 0.
"# $%$& www.ti.com SBAS203J − MARCH 2002 − REVISED JANUARY 2008 ELECTRICAL CHARACTERISTICS: AVDD = 5V (continued) All specifications from TMIN to TMAX, DVDD = +2.7V to 5.25V, fMOD = 15.625kHz, PGA = 1, Buffer ON, fDATA = 10Hz, Bipolar, and VREF ≡ (REF IN+) − (REF IN−) = +2.5V, unless otherwise noted.
"# $%$& www.ti.com SBAS203J − MARCH 2002 − REVISED JANUARY 2008 ELECTRICAL CHARACTERISTICS: AVDD = 3V All specifications from TMIN to TMAX, DVDD = +2.7V to 5.25V, fMOD = 15.625kHz, PGA = 1, Buffer ON, fDATA = 10Hz, Bipolar, and VREF ≡ (REF IN+) − (REF IN−) = +1.25V, unless otherwise noted. MSC1210Yx PARAMETER CONDITIONS MIN TYP MAX UNITS ANALOG INPUT (AIN0-AIN7, AINCOM) Analog Input Range Buffer OFF AGND − 0.1 AVDD + 0.1 V Buffer ON AGND + 50mV AVDD − 1.
"# $%$& www.ti.com SBAS203J − MARCH 2002 − REVISED JANUARY 2008 ELECTRICAL CHARACTERISTICS: AVDD = 3V (continued) All specifications from TMIN to TMAX, DVDD = +2.7V to 5.25V, fMOD = 15.625kHz, PGA = 1, Buffer ON, fDATA = 10Hz, Bipolar, and VREF ≡ (REF IN+) − (REF IN−) = +1.25V, unless otherwise noted.
"# $%$& www.ti.com SBAS203J − MARCH 2002 − REVISED JANUARY 2008 DIGITAL CHARACTERISTICS: DVDD = 2.7V to 5.25V All specifications from TMIN to TMAX, fOSC = 1MHz, unless otherwise specified. MSC1210Yx PARAMETER CONDITIONS MIN TYP MAX 2.7 UNITS DIGITAL POWER-SUPPLY REQUIREMENTS Digital Power-Supply Voltage DVDD 3.0 3.6 V Normal Mode, fOSC = 1MHz 1.4 1.6 mA Normal Mode, fOSC = 8MHz 8 9 mA Stop Mode(1) Digital Power-Supply Current DVDD µA 0.5 4.75 5.0 5.25 V 2 2.
"# $%$& www.ti.com SBAS203J − MARCH 2002 − REVISED JANUARY 2008 AC ELECTRICAL CHARACTERISTICS(1)(2): DVDD = 2.7V to 5.25V 2.7V to 3.6V SYMBOL 4.75V to 5.25V PARAMETER MIN MAX MIN MAX UNITS External Crystal Frequency (fOSC) External Clock Frequency (fOSC) External Ceramic Resonator Frequency (fOSC) 1 0 1 18 18 16 1 0 1 33 33 16 MHz MHz MHz FIGURE System Clock 1/tCLK(4) 4 Program Memory tLHLL 1 ALE Pulse Width 1.5tCLK − 5 1.5tCLK − 5 ns tAVLL 1 Address Valid to ALE LOW 0.
"# $%$& www.ti.com SBAS203J − MARCH 2002 − REVISED JANUARY 2008 EXPLANATION OF THE AC SYMBOLS Each Timing Symbol has five characters. The first character is always ‘t’ (= time). The other characters, depending on their positions, indicate the name of a signal or the logical status of that signal.
"# $%$& www.ti.com SBAS203J − MARCH 2002 − REVISED JANUARY 2008 ALE tWHLH PSEN tLLWL tWLWH WR tAVLL tLLAX tQ V W X tWHQX t DW PORT 0 A0−A7 from RI or DPL DATA OUT A0−A7 from PCL tAVWL PORT 2 P2.0−P2.7or A8−A15 from DPH A 8−A15 from PCH Figure 3. External Data Memory Write Cycle t HIGH VIH1 0.8V tf tr VIH1 0.8V VIH1 tLOW VIH1 0.8V t CLK Figure 4. External Clock Drive CLK 10 0.
"# $%$& www.ti.com SBAS203J − MARCH 2002 − REVISED JANUARY 2008 RESET AND POWER-ON TIMING tRW RST tRRD tRFD tRRD tRFD PSEN ALE t RS tRH EA NOTE: PSEN and ALE are internally pulled up with ~9kΩ during RST high. Figure 5. Reset Timing tRW RST tRFD tRRD PSEN tRS tRRD tRH ALE NOTE: PSEN and ALE are internally pulled up with ~9kΩ during RST high. Figure 6.
"# $%$& www.ti.com SBAS203J − MARCH 2002 − REVISED JANUARY 2008 PIN ASSIGNMENTS P0.3/AD3 P0.4/AD4 P0.5/AD5 58 P0.2/AD2 59 P0.1/AD1 P1.2/RxD1 60 P0.0/AD0 P1.3/TxD1 61 P1.0/T2 P1.4/INT2/SS 62 P1.1/T2EX P1.5/INT3/MOSI 63 DGND P1.6/INT4/MISO 64 DVDD P1.7/INT5/SCLK PAG PACKAGE TQFP-64 (TOP VIEW) 57 56 55 54 53 52 51 50 49 XOUT 1 48 EA XIN 2 47 P0.6/AD6 P3.0/RxD0 3 46 P0.7/AD7 P3.1/TxD0 4 45 ALE P3.2/INT0 5 44 PSEN/OSCCLK/MODCLK P3.3/INT1/TONE/PWM 6 43 P2.
"# $%$& www.ti.com SBAS203J − MARCH 2002 − REVISED JANUARY 2008 PIN DESCRIPTIONS PIN # NAME 1 XOUT 2 XIN 3−10 P3.0–P3.7 DESCRIPTION The crystal oscillator pin XOUT supports parallel resonant AT cut fundamental frequency crystals and ceramic resonators. XOUT serves as the output of the crystal amplifier. The crystal oscillator pin XIN supports parallel resonant AT cut fundamental frequency crystals and ceramic resonators.
"# $%$& www.ti.com SBAS203J − MARCH 2002 − REVISED JANUARY 2008 PIN DESCRIPTIONS (continued) PIN # NAME DESCRIPTION 44 PSEN, OSCCLK, MODCLK Program store enable. Connected to optional external memory as a chip enable. PSEN provides an active low pulse. In programming mode, PSEN is used as an input along with ALE to define serial or parallel programming mode. PSEN is held HIGH for parallel programming mode and LOW for serial programming.
"# $%$& www.ti.com SBAS203J − MARCH 2002 − REVISED JANUARY 2008 TYPICAL CHARACTERISTICS AVDD = +5V, DVDD = +5V, fOSC = 8MHz, PGA = 1, fMOD = 15.625Hz, Bipolar, Buffer ON, and VREF = (REF IN+) − (REF IN−) = +2.5V, unless otherwise specified.
"# $%$& www.ti.com SBAS203J − MARCH 2002 − REVISED JANUARY 2008 TYPICAL CHARACTERISTICS (Continued) AVDD = +5V, DVDD = +5V, fOSC = 8MHz, PGA = 1, fMOD = 15.625Hz, Bipolar, Buffer ON, and VREF = (REF IN+) − (REF IN−) = +2.5V, unless otherwise specified. FAST SETTLING FILTER EFFECTIVE NUMBER OF BITS vs DECIMATION RATIO EFFECTIVE NUMBER OF BITS vs fMOD (set with ACLK) 20 25 19 Gain 1 18 fMOD = 203kHz 20 Gain 16 16 ENOB (rms) ENOB 17 15 14 Gain 128 13 12 fMOD = 15.
"# $%$& www.ti.com SBAS203J − MARCH 2002 − REVISED JANUARY 2008 TYPICAL CHARACTERISTICS (Continued) AVDD = +5V, DVDD = +5V, fOSC = 8MHz, PGA = 1, fMOD = 15.625Hz, Bipolar, Buffer ON, and VREF = (REF IN+) − (REF IN−) = +2.5V, unless otherwise specified. INTEGRAL NONLINEARITY vs INPUT SIGNAL INTEGRAL NONLINEARITY vs INPUT SIGNAL 10 30 VREF = AVDD, Buffer OFF 8 20 −40_ C 4 2 INL (ppm of FS) INL (ppm of FS) 6 +85_C 0 −2 +25_ C −4 −6 10 0 −10 −20 −8 −10 −2.5 −2 −1.5 −1 −0.5 0 0.5 1 1.
"# $%$& www.ti.com SBAS203J − MARCH 2002 − REVISED JANUARY 2008 TYPICAL CHARACTERISTICS (Continued) AVDD = +5V, DVDD = +5V, fOSC = 8MHz, PGA = 1, fMOD = 15.625Hz, Bipolar, Buffer ON, and VREF = (REF IN+) − (REF IN−) = +2.5V, unless otherwise specified. VREFOUT vs LOAD CURRENT 2.510 4000 2.508 3500 2.506 3000 2.504 VREFOUT (V) Number of Occurrences HISTOGRAM OF OUTPUT DATA 4500 2500 2000 1500 2.502 2.500 2.498 2.496 1000 2.494 500 2.492 0 −2 −1.5 −1 −0.5 2.490 0 0.5 1 1.
"# $%$& www.ti.com SBAS203J − MARCH 2002 − REVISED JANUARY 2008 TYPICAL CHARACTERISTICS (Continued) AVDD = +5V, DVDD = +5V, fOSC = 8MHz, PGA = 1, fMOD = 15.625Hz, Bipolar, Buffer ON, and VREF = (REF IN+) − (REF IN−) = +2.5V, unless otherwise specified. DIGITAL SUPPLY CURRENT vs SUPPLY VOLTAGE NORMALIZED GAIN vs PGA 101 +85°C 100 15 −40°C +25°C Buffer OFF Normalized Gain (%) 10 5 99 98 Buffer ON 97 0 96 2.5 3.0 3.5 4.0 4.5 5.0 5.
"# $%$& www.ti.com SBAS203J − MARCH 2002 − REVISED JANUARY 2008 The microcontroller core is 8051 instruction set compatible. The microcontroller core is an optimized 8051 core that executes up to three times faster than the standard 8051 core, given the same clock source. That makes it possible to run the device at a lower external clock frequency and achieve the same performance at lower power than the standard 8051 core.
"# $%$& www.ti.com SBAS203J − MARCH 2002 − REVISED JANUARY 2008 ENHANCED 8051 CORE MSC121 Timing Single−Byte, Single−Cycle Instruction ALE PSEN 0 AD0−AD7 PORT 2 4 Cycles CLK 12 Cycles Standard 8051 Timing All instructions in the MSC1210 family perform exactly the same functions as they would in a standard 8051. The effect on bits, flags, and registers is the same. However, the timing is different.
"# $%$& www.ti.com SBAS203J − MARCH 2002 − REVISED JANUARY 2008 MSC1210Y5. This gives the user the ability to add or subtract software functions and to freely migrate between family members. Thus, the MSC1210 can become a standard device used across several application platforms. Furthermore, improvements were made to peripheral features that off-load processing from the core, and the user, to further improve efficiency.
"# $%$& www.ti.com SBAS203J − MARCH 2002 − REVISED JANUARY 2008 it is possible to have up to eight fully differential input channels. It is also possible to switch the polarity of the differential input pair to negate any offset voltages. OVERVIEW The MSC1210 ADC structure is shown in Figure 12. The figure lists the components that make up the ADC, along with the corresponding special function register (SFR) associated with each component.
"# $%$& www.ti.com SBAS203J − MARCH 2002 − REVISED JANUARY 2008 The input impedance of the MSC1210 without the buffer is 7MΩ/PGA. The buffer is controlled by the state of the BUF bit in the ADC control register (ADCON0 DCh). AIN 0 ADC ANALOG INPUT AIN 1 When the buffer is not selected, the input impedance of the analog input changes with ACLK clock frequency (ACLK F6h) and gain (PGA).
"# $%$& www.ti.com SBAS203J − MARCH 2002 − REVISED JANUARY 2008 ADC PGA The PGA can be set to gains of 1, 2, 4, 8, 16, 32, 64, or 128. Using the PGA can actually improve the effective resolution of the ADC. For instance, with a PGA of 1 on a ±2.5V full-scale range, the ADC can resolve to 1.5µV. With a PGA of 128 on a ±19mV full-scale range, the ADC can resolve to 75nV, as shown in Table 2. Table 2.
"# $%$& www.ti.com SBAS203J − MARCH 2002 − REVISED JANUARY 2008 This combines the low-noise advantage of the Sinc3 filter with the quick response of the Fast Settling Time filter. The frequency response of each filter is shown in Figure 16. SINC3 FILTER RESPONSE (−3dB = 0.262 • fDATA) 0 VOLTAGE REFERENCE −20 −40 Gain (dB) The MSC1210 can use either an internal or external voltage reference. The voltage reference selection is controlled via ADC Control Register 0 (ADCON0, SFR DCh).
"# $%$& www.ti.com SBAS203J − MARCH 2002 − REVISED JANUARY 2008 RESET POWER-ON RESET The device can be reset from the following sources: The on-chip power-on reset (POR) circuitry releases the device from reset at approximately DVDD = 2.0V. The POR accommodates power-supply ramp rates as slow as 1V/10ms. To ensure proper operation, the power supply should ramp monotonically.
"# $%$& www.ti.com SBAS203J − MARCH 2002 − REVISED JANUARY 2008 IDLE MODE POWER CONSUMPTION CONSIDERATIONS Idle mode is entered by setting the IDLE bit in the Power Control register (PCON, 087h). In Idle mode, the CPU, Timer0, Timer1, and USARTs are stopped, but all other peripherals and digital pins remain active. The device can be returned to active mode via an active internal or external interrupt. This mode is typically used for reducing power consumption between ADC samples.
"# $%$& www.ti.com SBAS203J − MARCH 2002 − REVISED JANUARY 2008 FLASH MEMORY The page size for Flash memory is 128 bytes. The respective page must be erased before it can be written to, regardless of whether it is mapped to Program or Data Memory space. The MSC1210 uses a memory addressing scheme that separates Program Memory (FLASH/ROM) from Data Memory (FLASH/RAM). Each area is 64kB beginning at address 0000h and ending at FFFFh, as shown in Figure 18.
"# $%$& www.ti.com SBAS203J − MARCH 2002 − REVISED JANUARY 2008 The MSC1210 allows the user to partition the Flash Memory between Program Memory and Data Memory. For instance, the MSC1210Y5 contains 32kB of Flash Memory on-chip. Through the HW configuration registers, the user can define the partition between Program Memory (PM) and Data Memory (DM), as shown in Table 3 and Table 4. The MSC1210 family offers four memory configurations, as shown. Table 3.
"# $%$& www.ti.com SBAS203J − MARCH 2002 − REVISED JANUARY 2008 CONFIGURATION MEMORY The MSC1210 Configuration Memory consists of 128 bytes. In UAM, all Configuration Memory is readable using the faddr_data_read Boot ROM routine, and the CADDR and CDATA registers. In UAM, however, none of the Configuration Memory is writable. be accessed indirectly. Thus, a direct reference to one of the upper 128 locations must be an SFR access. Direct RAM is reached at locations 0 to 7Fh (0 to 127).
"# $%$& www.ti.com SBAS203J − MARCH 2002 − REVISED JANUARY 2008 through R7. Since there are four banks, the currently selected bank will be used by any instruction using R0—R7. This allows software to change context by simply switching banks. This is controlled via the Program Status Word register (PSW; 0D0h) in the SFR area described below. Registers R0 and R1 also allow their contents to be used for indirect addressing of the upper 128 bytes of RAM.
"# $%$& www.ti.com SBAS203J − MARCH 2002 − REVISED JANUARY 2008 Table 6.
"# $%$& www.ti.com SBAS203J − MARCH 2002 − REVISED JANUARY 2008 ACCESSING EXTERNAL MEMORY If external memory is used, P0 and P2 can be configured as address and data lines. If external memory is not used, P0 and P2 can be configured as general-purpose I/O lines through the Hardware Configuration Register. To enable access to external memory, bits 0 and 1 of the HCR1 register must be set to 0.
"# $%$& www.ti.com SBAS203J − MARCH 2002 − REVISED JANUARY 2008 The MSC1210 is shipped with Flash Memory erased (all 1s). Parallel programming methods typically involve a third-party programmer. Serial programming methods typically involve in-system programming. UAM allows Flash Program and Data Memory programming. The actual code for Flash programming cannot execute from Flash. That code must execute from the Boot ROM, internal (von Neumann) RAM or external memory.
"# $%$& www.ti.com SBAS203J − MARCH 2002 − REVISED JANUARY 2008 INTERRUPTS HARDWARE CONFIGURATION MEMORY The MSC1210 uses a three-priority interrupt system. As shown in Table 7, each interrupt source has an independent priority bit, flag, interrupt vector, and enable (except that nine interrupts share the Auxiliary Interrupt [AI] at the highest priority). In addition, interrupts can be globally enabled or disabled. The interrupt structure is compatible with the original 8051 family.
"# $%$& www.ti.com SBAS203J − MARCH 2002 − REVISED JANUARY 2008 Hardware Configuration Register 0 (HCR0)—Accessed Using SFR Registers CADDR and CDATA. CADDR 7Fh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 EPMA PML RSL EBR EWDR DFSEL2 DFSEL1 DFSEL0 NOTE: HCR0 is programmable only in Flash Programming mode, but can be read in User Application mode using the CADDR and CDATA SFRs or the faddr_data_read Boot ROM routine. EPMA bit 7 Enable Programming Memory Access (Security Bit).
"# $%$& www.ti.com SBAS203J − MARCH 2002 − REVISED JANUARY 2008 Hardware Configuration Register 1 (HCR1) CADDR 7Eh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 DBLSEL1 DBLSEL0 ABLSEL1 ABLSEL0 DAB DDB EGP0 EGP23 NOTE: HCR1 is programmable only in Flash Programming mode, but can be read in User Application mode using the CADDR and CDATA SFRs or the faddr_data_read Boot ROM routine. DBLSEL bits 7−6 Digital Brownout Level Select 00: 4.5V 01: 4.2V 10: 2.7V 11: 2.
"# $%$& www.ti.com SBAS203J − MARCH 2002 − REVISED JANUARY 2008 SFR Definitions (Boldface definitions indicate that the register is unique to the MSC1210Yx) ADDRESS REGISTER BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 RESET VALUES 80h P0 P0.7 P0.6 P0.5 P0.4 P0.3 P0.2 P0.1 P0.
"# $%$& www.ti.com SBAS203J − MARCH 2002 − REVISED JANUARY 2008 SFR Definitions (continued) (Boldface definitions indicate that the register is unique to the MSC1210Yx) ADDRESS REGISTER BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 RESET VALUES AEh P1DDRL P13H P13L P12H P12L P11H P11L P10H P10L 00h AFh P1DDRH P17H P17L P16H P16L P15H P15L P14H P14L 00h B0h P3 P3.7 RD P3.6 WR P3.5 T1 P3.4 T0 P3.3 INT1 P3.2 INT0 P3.1 TXD0 P3.
"# $%$& www.ti.
"# $%$& www.ti.com SBAS203J − MARCH 2002 − REVISED JANUARY 2008 Table 8. Special Function Register Cross Reference SFR ADDRESS FUNCTIONS CPU INTERRUPTS PORTS SERIAL COMM.
"# $%$& www.ti.com SBAS203J − MARCH 2002 − REVISED JANUARY 2008 Table 8. Special Function Register Cross Reference (continued) SFR ADDRESS FUNCTIONS CPU INTERRUPTS PORTS SERIAL COMM.
"# $%$& www.ti.com SBAS203J − MARCH 2002 − REVISED JANUARY 2008 Table 8. Special Function Register Cross Reference (continued) SFR ADDRESS FUNCTIONS CPU INTERRUPTS PORTS SERIAL COMM.
"# $%$& www.ti.com SBAS203J − MARCH 2002 − REVISED JANUARY 2008 Port 0 (P0) SFR 80h P0.7−0 bits 7−0 7 6 5 4 3 2 1 0 Reset Value P0.7 P0.6 P0.5 P0.4 P0.3 P0.2 P0.1 P0.0 FFh Port 0. This port functions as a multiplexed address/data bus during external memory access, and as a generalpurpose I/O port when external memory access is not needed. During external memory cycles, this port will contain the LSB of the address when ALE is HIGH, and Data when ALE is LOW.
"# $%$& www.ti.com SBAS203J − MARCH 2002 − REVISED JANUARY 2008 Data Pointer High 1 (DPH1) SFR 85h DPH1.7−0 bits 7−0 7 6 5 4 3 2 1 0 Reset Value DPH1.7 DPH1.6 DPH1.5 DPH1.4 DPH1.3 DPH1.2 DPH1.1 DPH1.0 00h Data Pointer High. This register is the high byte of the auxiliary 16-bit data pointer. When the SEL bit (DPS.0, SFR 86h) is set, DPL1 and DPH1 are used in place of DPL0 and DPH0 during DPTR operations.
"# $%$& www.ti.com SBAS203J − MARCH 2002 − REVISED JANUARY 2008 Timer/Counter Control (TCON) SFR 88h 7 6 5 4 3 2 1 0 Reset Value TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 00h TF1 bit 7 Timer 1 Overflow Flag. This bit indicates when Timer 1 overflows its maximum count as defined by the current mode. This bit can be cleared by software and is automatically cleared when the CPU vectors to the Timer 1 interrupt service routine. 0: No Timer 1 overflow has been detected.
"# $%$& www.ti.com SBAS203J − MARCH 2002 − REVISED JANUARY 2008 Timer Mode Control (TMOD) 7 6 5 4 3 2 TIMER 1 SFR 89h GATE C/T 1 0 M1 M0 Reset Value 00h TIMER 0 M1 M0 GATE C/T GATE bit 7 Timer 1 Gate Control. This bit enables/disables the ability of Timer 1 to increment. 0: Timer 1 will clock when TR1 = 1, regardless of the state of pin INT1. 1: Timer 1 will clock only when TR1 = 1 and pin INT1 = 1. C/T bit 6 Timer 1 Counter/Timer Select. 0: Timer is incremented by internal clocks.
"# $%$& www.ti.com SBAS203J − MARCH 2002 − REVISED JANUARY 2008 Timer 0 MSB (TH0) SFR 8Ch TH0.7−0 bits 7−0 7 6 5 4 3 2 1 0 Reset Value TH0.7 TH0.6 TH0.5 TH0.4 TH0.3 TH0.2 TH0.1 TH0.0 00h Timer 0 MSB. This register contains the most significant byte of Timer 0. Timer 1 MSB (TH1) SFR 8Dh TH1.7−0 bits 7−0 7 6 5 4 3 2 1 0 Reset Value TH1.7 TH1.6 TH1.5 TH1.4 TH1.3 TH1.2 TH1.1 TH1.0 00h Timer 1 MSB. This register contains the most significant byte of Timer 1.
"# $%$& www.ti.com SBAS203J − MARCH 2002 − REVISED JANUARY 2008 Memory Write Select (MWS) SFR 8Fh MXWS bit 0 7 6 5 4 3 2 1 0 Reset Value 0 0 0 0 0 0 0 MXWS 00h MOVX Write Select. This allows writing to the internal Flash program memory. 0: No writes are allowed to the internal Flash program memory. 1: Writing is allowed to the internal Flash program memory, unless PML (HCR0) or RSL (HCR0) are on. Port 1 (P1) SFR 90h 7 6 5 4 3 2 1 0 Reset Value P1.7 INT5/SCK P1.
"# $%$& www.ti.com SBAS203J − MARCH 2002 − REVISED JANUARY 2008 External Interrupt Flag (EXIF) SFR 91h 7 6 5 4 3 2 1 0 Reset Value IE5 IE4 IE3 IE2 1 0 0 0 08h IE5 bit 7 External Interrupt 5 Flag. This bit will be set when a falling edge is detected on INT5. This bit must be cleared manually by software. Setting this bit in software will cause an interrupt if enabled. IE4 bit 6 External Interrupt 4 Flag. This bit will be set when a rising edge is detected on INT4.
"# $%$& www.ti.com SBAS203J − MARCH 2002 − REVISED JANUARY 2008 Memory Control (MCON) SFR 95h 7 6 5 4 3 2 1 0 Reset Value BPSEL 0 0 — — — — RAMMAP 00h BPSEL bit 7 Breakpoint Address Selection Write: Select one of two Breakpoint registers: 0 or 1. 0: Select breakpoint register 0. 1: Select breakpoint register 1. Read: Provides the Breakpoint register that created the last interrupt: 0 or 1. RAMMAP bit 0 Memory Map 1kB extended SRAM.
"# $%$& www.ti.com SBAS203J − MARCH 2002 − REVISED JANUARY 2008 Serial Data Buffer 0 (SBUF0) 7 6 5 4 3 2 1 0 SFR 99h SBUF0 bits 7−0 Reset Value 00h Serial Data Buffer 0. Data for Serial Port 0 is read from or written to this location. The serial transmit and receive buffers are separate registers, but both are addressed at this location. SPI Control (SPICON). Any change resets the SPI interface, counters, and pointers. PDCON controls which is enabled.
"# $%$& www.ti.com SBAS203J − MARCH 2002 − REVISED JANUARY 2008 SPI Transmit Control Register (SPITCON) 7 6 SFR 9Dh 5 4 3 CLK_EN DRV_DLY DRV_EN CLK_EN bit 5 SCK Driver Enable. 0: Disable SCK Driver (Master Mode) 1: Enable SCK Driver (Master Mode) DRV_DLY bit 4 Drive Delay. (Refer to DRV_EN bit) 0: Drive output immediately 1: Drive output after current byte transfer DRV_EN bit 3 Drive Enable.
"# $%$& www.ti.com SBAS203J − MARCH 2002 − REVISED JANUARY 2008 Tone Low (TONELOW)/PWM Low (PWMLOW) SFR A2h 7 6 5 4 3 2 1 0 Reset Value TDIV7 PWM7 TDIV6 PWM6 TDIV5 PWM5 TDIV4 PWM4 TDIV3 PWM3 TDIV2 PWM2 TDIV1 PWM1 TDIV0 PWM0 00h TDIV7−0 bits 7−0 Tone Divisor. The low order bits that define the half-time period. For staircase mode the output is high impedance for the last 1/4 of this period. PWMLOW bits 7−0 Pulse Width Modulator Low Bits.
"# $%$& www.ti.com SBAS203J − MARCH 2002 − REVISED JANUARY 2008 Auxiliary Interrupt Enable (AIE) SFR A6h 7 6 5 4 3 2 1 0 Reset Value ESEC ESUM EADC EMSEC ESPIT ESPIR EALV EDLVB 00h Interrupts are enabled by EICON.4 (SFR D8H). The other interrupts are controlled by the IE and EIE registers. ESEC bit 7 Enable Seconds Timer Interrupt (lowest priority auxiliary interrupt). Write: Set mask bit for this interrupt 0 = masked, 1 = enabled.
"# $%$& www.ti.com SBAS203J − MARCH 2002 − REVISED JANUARY 2008 Auxiliary Interrupt Status Register (AISTAT) SFR A7h 7 6 5 4 3 2 1 0 Reset Value SEC SUM ADC MSEC SPIT SPIR ALVD DLVD 00h SEC bit 7 Second System Timer Interrupt Status Flag (lowest priority AI). 0: SEC interrupt inactive or masked. 1: SEC Interrupt active. (It is set inactive by reading the SECINT register.) SUM bit 6 Summation Register Interrupt Status Flag. 0: SUM interrupt inactive or masked. 1: SUM interrupt active.
"# $%$& www.ti.com SBAS203J − MARCH 2002 − REVISED JANUARY 2008 Interrupt Enable (IE) SFR A8h 7 6 5 4 3 2 1 0 Reset Value EA ES1 ET2 ES0 ET1 EX1 ET0 EX0 00h EA bit 7 Global Interrupt Enable. This bit controls the global masking of all interrupts except those in AIE (SFR A6h). 0: Disable interrupt sources. This bit overrides individual interrupt mask settings for this register. 1: Enable all individual interrupt masks. Individual interrupts in this register will occur if enabled.
"# $%$& www.ti.com SBAS203J − MARCH 2002 − REVISED JANUARY 2008 Breakpoint Control (BPCON) SFR A9h 7 6 5 4 3 2 1 0 Reset Value BP 0 0 0 0 0 PMSEL EBP 00h Writing to register sets the breakpoint condition specified by MCON, BPL, and BPH. BP bit 7 Breakpoint Interrupt. This bit indicates that a break condition has been recognized by a hardware breakpoint register(s). Read: Status of Breakpoint Interrupt. Will indicate a breakpoint match for any of the breakpoint registers.
"# $%$& www.ti.com SBAS203J − MARCH 2002 − REVISED JANUARY 2008 Port 0 Data Direction Low Register (P0DDRL) SFR ACh P0.3 bits 7−6 P0.2 bits 5−4 P0.1 bits 3−2 P0.0 bits 1−0 7 6 5 4 3 2 1 0 Reset Value P03H P03L P02H P02L P01H P01L P00H P00L 00h Port 0 Bit 3 Control. P03H P03L 0 0 Standard 8051 (Pull-Up) 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input Port 0 Bit 2 Control.
"# $%$& www.ti.com SBAS203J − MARCH 2002 − REVISED JANUARY 2008 Port 0 Data Direction High Register (P0DDRH) SFR ADh P0.7 bits 7−6 P0.6 bits 5−4 P0.5 bits 3−2 P0.4 bits 1−0 7 6 5 4 3 2 1 0 Reset Value P07H P07L P06H P06L P05H P05L P04H P04L 00h Port 0 Bit 7 Control. P07H P07L 0 0 Standard 8051 (Pull-Up) 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input Port 0 Bit 6 Control.
"# $%$& www.ti.com SBAS203J − MARCH 2002 − REVISED JANUARY 2008 Port 1 Data Direction Low Register (P1DDRL) SFR AEh P1.3 bits 7−6 P1.2 bits 5−4 P1.1 bits 3−2 P1.0 bits 1−0 62 7 6 5 4 3 2 1 0 Reset Value P13H P13L P12H P12L P11H P11L P10H P10L 00h Port 1 Bit 3 Control. P13H P13L 0 0 Standard 8051 (Pull-Up) 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input Port 1 Bit 2 Control.
"# $%$& www.ti.com SBAS203J − MARCH 2002 − REVISED JANUARY 2008 Port 1 Data Direction High Register (P1DDRH) SFR AFh P1.7 bits 7−6 P1.6 bits 5−4 P1.5 bits 3−2 P1.4 bits 1−0 7 6 5 4 3 2 1 0 Reset Value P17H P17L P16H P16L P15H P15L P14H P14L 00h Port 1 Bit 7 Control. P17H P17L 0 0 Standard 8051 (Pull-Up) 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input Port 1 Bit 6 Control.
"# $%$& www.ti.com SBAS203J − MARCH 2002 − REVISED JANUARY 2008 Port 3 (P3) SFR B0h 7 6 5 4 3 2 1 0 Reset Value P3.7 RD P3.6 WR P3.5 T1 P3.4 T0 P3.3 INT1 P3.2 INT0 P3.1 TXD0 P3.0 RXD0 FFh P3.7−0 bits 7−0 General-Purpose I/O Port 3. This register functions as a general-purpose I/O port. In addition, all the pins have an alternative function listed below. Each of the functions is controlled by several other SFRs.
"# $%$& www.ti.com SBAS203J − MARCH 2002 − REVISED JANUARY 2008 Port 2 Data Direction Low Register (P2DDRL) SFR B1h P2.3 bits 7−6 P2.2 bits 5−4 P2.1 bits 3−2 P2.0 bits 1−0 7 6 5 4 3 2 1 0 Reset Value P23H P23L P22H P22L P21H P21L P20H P20L 00h Port 2 Bit 3 Control. P23H P23L 0 0 Standard 8051 (Pull-Up) 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input Port 2 Bit 2 Control.
"# $%$& www.ti.com SBAS203J − MARCH 2002 − REVISED JANUARY 2008 Port 2 Data Direction High Register (P2DDRH) SFR B2h P2.7 bits 7−6 P2.6 bits 5−4 P2.5 bits 3−2 P2.4 bits 1−0 7 6 5 4 3 2 1 0 Reset Value P27H P27L P26H P26L P25H P25L P24H P24L 00h Port 2 Bit 7 Control. P27H P27L 0 0 Standard 8051 (Pull-Up) 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input Port 2 Bit 6 Control.
"# $%$& www.ti.com SBAS203J − MARCH 2002 − REVISED JANUARY 2008 Port 3 Data Direction Low Register (P3DDRL) SFR B3h P3.3 bits 7−6 P3.2 bits 5−4 P3.1 bits 3−2 P3.0 bits 1−0 7 6 5 4 3 2 1 0 Reset Value P33H P33L P32H P32L P31H P31L P30H P30L 00h Port 3 Bit 3 Control. P33H P33L 0 0 Standard 8051 (Pull-Up) 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input Port 3 Bit 2 Control.
"# $%$& www.ti.com SBAS203J − MARCH 2002 − REVISED JANUARY 2008 Port 3 Data Direction High Register (P3DDRH) SFR B4h P3.7 bits 7−6 7 6 5 4 3 2 1 0 Reset Value P37H P37L P36H P36L P35H P35L P34H P34L 00h Port 3 Bit 7 Control. P37H P37L 0 0 Standard 8051 (Pull-Up) 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input NOTE: Port 3.7 also controlled by EA and Memory Access Control HCR1.1. P3.6 bits 5−4 Port 3 Bit 6 Control.
"# $%$& www.ti.com SBAS203J − MARCH 2002 − REVISED JANUARY 2008 Interrupt Priority (IP) SFR B8h 7 6 5 4 3 2 1 0 Reset Value 1 PS1 PT2 PS0 PT1 PX1 PT0 PX0 80h PS1 bit 6 Serial Port 1 Interrupt. This bit controls the priority of the serial Port 1 interrupt. 0 = Serial Port 1 priority is determined by the natural priority order. 1 = Serial Port 1 is a high priority interrupt. PT2 bit 5 Timer 2 Interrupt. This bit controls the priority of the Timer 2 interrupt.
"# $%$& www.ti.com SBAS203J − MARCH 2002 − REVISED JANUARY 2008 Serial Port 1 Control (SCON1) SFR C0h SM0−2 bits 7−5 7 6 5 4 3 2 1 0 Reset Value SM0_1 SM1_1 SM2_1 REN_1 TB8_1 RB8_1 TI_1 RI_1 00h Serial Port 1 Mode. These bits control the mode of serial Port 1. Modes 1, 2, and 3 have 1 start and 1 stop bit in addition to the 8 or 9 data bits.
"# $%$& www.ti.com SBAS203J − MARCH 2002 − REVISED JANUARY 2008 Serial Data Buffer 1 (SBUF1) 7 6 5 4 3 2 1 0 SFR C1h Reset Value 00h SBUF1.7−0 Serial Data Buffer 1. Data for serial Port 1 is read from or written to this location. The serial transmit and receive bits 7−0 buffers are separate registers, but both are addressed at this location.
"# $%$& www.ti.com SBAS203J − MARCH 2002 − REVISED JANUARY 2008 Timer 2 Control (T2CON) SFR C8h 7 6 5 4 3 2 1 0 Reset Value TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2 CP/RL2 00h TF2 bit 7 Timer 2 Overflow Flag. This flag will be set when Timer 2 overflows from FFFFh. It must be cleared by software. TF2 will only be set if RCLK and TCLK are both cleared to 0. Writing a 1 to TF2 forces a Timer 2 interrupt if enabled. EXF2 bit 6 Timer 2 External Flag. A negative transition on the T2EX pin (P1.
"# $%$& www.ti.com SBAS203J − MARCH 2002 − REVISED JANUARY 2008 Timer 2 Capture MSB (RCAP2H) 7 6 5 4 3 2 1 0 Reset Value SFR CBh RCAP2H bits 7−0 00h Timer 2 Capture MSB. This register is used to capture the TH2 value when Timer 2 is configured in capture mode. RCAP2H is also used as the MSB of a 16-bit reload value when Timer 2 is configured in auto-reload mode. Timer 2 LSB (TL2) 7 6 5 4 3 2 1 0 Reset Value SFR CCh TL2 bits 7−0 00h Timer 2 LSB.
"# $%$& www.ti.com SBAS203J − MARCH 2002 − REVISED JANUARY 2008 ADC Offset Calibration Register Low Byte (OCL) 7 6 5 4 3 2 1 SFR D1h OCL bits 7−0 0 Reset Value LSB 00h ADC Offset Calibration Register Low Byte. This is the low byte of the 24-bit word that contains the ADC offset calibration. A value that is written to this location will set the ADC offset calibration value.
"# $%$& www.ti.com SBAS203J − MARCH 2002 − REVISED JANUARY 2008 ADC Multiplexer Register (ADMUX) SFR D7h INP3−0 bits 7−4 INN3−0 bits 3−0 7 6 5 4 3 2 1 0 Reset Value INP3 INP2 INP1 INP0 INN3 INN2 INN1 INN0 01h Input Multiplexer Positive Channel. This selects the positive signal input.
"# $%$& www.ti.com SBAS203J − MARCH 2002 − REVISED JANUARY 2008 Enable Interrupt Control (EICON) SFR D8h 7 6 5 4 3 2 1 0 Reset Value SMOD1 1 EAI AI WDTI 0 0 0 40h SMOD1 bit 7 Serial Port 1 Mode. When this bit is set the serial baud rate for Port 1 will be doubled. 0 = Standard baud rate for Port 1 (default). 1 = Double baud rate for Port 1. EAI bit 5 Enable Auxiliary Interrupt.
"# $%$& www.ti.com SBAS203J − MARCH 2002 − REVISED JANUARY 2008 ADC Control Register 0 (ADCON0) 7 SFR DCh 6 5 4 3 2 1 0 Reset Value BOD EVREF VREFH EBUF PGA2 PGA1 PGA0 30h BOD bit 6 Burnout Detect. When enabled this connects a positive current source to the positive channel and a negative current source to the negative channel. If the channel is open circuit then the ADC results will be full-scale. 0 = Burnout Current Sources Off (default). 1 = Burnout Current Sources On.
"# $%$& www.ti.com SBAS203J − MARCH 2002 − REVISED JANUARY 2008 ADC Control Register 1 (ADCON1) SFR DDh POL bit 6 7 6 5 4 3 2 1 0 Reset Value — POL SM1 SM0 — CAL2 CAL1 CAL0 0000 0000b Polarity. Polarity of the ADC result and Summation register. 0 = Bipolar. 1 = Unipolar. The LSB size is 1/2 the size of bipolar (twice the resolution).
"# $%$& www.ti.com SBAS203J − MARCH 2002 − REVISED JANUARY 2008 Accumulator (A or ACC) SFR E0h ACC.7−0 bits 7−0 7 6 5 4 3 2 1 0 Reset Value ACC.7 ACC.6 ACC.5 ACC.4 ACC.3 ACC.2 ACC.1 ACC.0 00h Accumulator. This register serves as the accumulator for arithmetic and logic operations. Summation/Shifter Control (SSCON) SFR E1h 7 6 5 4 3 2 1 0 Reset Value SSCON1 SSCON0 SCNT2 SCNT1 SCNT0 SHF2 SHF1 SHF0 00h The Summation register is powered down when the ADC is powered down.
"# $%$& www.ti.com SBAS203J − MARCH 2002 − REVISED JANUARY 2008 Summation Register 0 (SUMR0) 7 6 5 4 3 2 1 SFR E2h SUMR0 bits 7−0 0 Reset Value LSB 00h Summation Register 0. This is the least significant byte of the 32-bit summation register or bits 0 to 7. Write: Will cause values in SUMR3−0 to be added to the summation register. Read: Will clear the Summation Count Interrupt. AI in EICON (SFR D8h) must also be cleared.
"# $%$& www.ti.com SBAS203J − MARCH 2002 − REVISED JANUARY 2008 Low Voltage Detect Control (LVDCON) SFR E7h 7 6 5 4 3 2 1 0 Reset Value ALVDIS ALVD2 ALVD1 ALVD0 DLVDIS DLVD2 DLVD1 DLVD0 00h NOTE: By default, both analog and digital low-voltage detections are enabled, which causes approximately 25µA of current consumption from the power supply. To minimize this power consumption, both low-voltage detections should be disabled before entering Stop mode.
"# $%$& www.ti.com SBAS203J − MARCH 2002 − REVISED JANUARY 2008 Extended Interrupt Enable (EIE) SFR E8h 7 6 5 4 3 2 1 0 Reset Value 1 1 1 EWDI EX5 EX4 EX3 EX2 E0h EWDI bit 4 Enable Watchdog Interrupt. This bit enables/disables the watchdog interrupt. The Watchdog timer is enabled by (SFR FFh) and PDCON (SFR F1h) registers. 0 = Disable the Watchdog Interrupt 1 = Enable Interrupt Request Generated by the Watchdog Timer EX5 bit 3 External Interrupt 5 Enable.
"# $%$& www.ti.com SBAS203J − MARCH 2002 − REVISED JANUARY 2008 Hardware Version Register (HDWVER) 7 6 5 4 3 2 1 0 Reset Value SFR EBh Flash Memory Control (FMCON) SFR EEh 7 6 5 4 3 2 1 0 Reset Value 0 PGERA 0 FRCM 0 BUSY 1 0 02h PGERA bit 6 Page Erase. 0 = MOVX to Flash will perform a byte write operation 1 = MOVX to Flash will perform a page erase operation FRCM bit 4 Frequency Control Mode. 0 = Bypass (default) 1 = Use Delay Line.
"# $%$& www.ti.com SBAS203J − MARCH 2002 − REVISED JANUARY 2008 Power-Down Control Register (PDCON) SFR F1h 7 6 5 4 3 2 1 0 Reset Value 0 0 0 PDPWM PDADC PDWDT PDST PDSPI 1Fh Turning peripheral modules off puts the MSC1210 in the lowest power mode. PDPWM bit 4 Pulse Width Module Control. 0 = PWM On 1 = PWM Power Down PDADC bit 3 ADC Control. 0 = ADC On 1 = ADC, VREF, and summation registers are powered down. PDWDT bit 2 Watchdog Timer Control.
"# $%$& www.ti.com SBAS203J − MARCH 2002 − REVISED JANUARY 2008 Analog Clock (ACLK) SFR F6h 7 6 5 4 3 2 1 0 Reset Value 0 FREQ6 FREQ5 FREQ4 FREQ3 FREQ2 FREQ1 FREQ0 03h FREQ6−0 Clock Frequency − 1. This value + 1 divides the system clock to create the ADC clock.
"# $%$& www.ti.com SBAS203J − MARCH 2002 − REVISED JANUARY 2008 Seconds Timer Interrupt (SECINT) SFR F9h 7 6 5 4 3 2 1 0 Reset Value WRT SECINT6 SECINT5 SECINT4 SECINT3 SECINT2 SECINT1 SECINT0 7Fh This system clock is divided by the value of the 16-bit register MSECH:MSECL. Then, the 1ms timer tick is divided by the register HMSEC that provides the 100ms signal used by this seconds timer. Therefore, the seconds timer can generate an interrupt that occurs from 100ms to 12.8 seconds.
"# $%$& www.ti.com SBAS203J − MARCH 2002 − REVISED JANUARY 2008 One Millisecond High Register (MSECH) SFR FDh 7 6 5 4 3 2 1 0 Reset Value MSECH7 MSECH6 MSECH5 MSECH4 MSECH3 MSECH2 MSECH1 MSECH0 0Fh MSECH7−0 One Millisecond High. This value in combination with the previous register is used to create a 1ms clock.
www.ti.com SBAS203J − MARCH 2002 − REVISED JANUARY 2008 Revision History DATE REV PAGE SECTION DESCRIPTION 1/08 J 70 Serial Port Mode 1 Deleted note (2) from SM0−2 table. 10/07 I 26 Voltage Reference Added paragraph to end of section. NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
PACKAGE OPTION ADDENDUM www.ti.
PACKAGE OPTION ADDENDUM www.ti.com 10-Jul-2009 (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information.
PACKAGE MATERIALS INFORMATION www.ti.com 10-Jul-2009 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing MSC1210Y2PAGR TQFP PAG 64 SPQ Reel Reel Diameter Width (mm) W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 1500 330.0 24.8 13.0 13.0 1.5 16.0 24.0 Q2 MSC1210Y2PAGT TQFP PAG 64 250 330.0 24.8 13.0 13.0 1.5 16.0 24.0 Q2 MSC1210Y3PAGR TQFP PAG 64 1000 330.0 24.8 13.0 13.0 1.5 16.0 24.
PACKAGE MATERIALS INFORMATION www.ti.com 10-Jul-2009 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) MSC1210Y2PAGR TQFP PAG 64 1500 346.0 346.0 41.0 MSC1210Y2PAGT TQFP PAG 64 250 346.0 346.0 41.0 MSC1210Y3PAGR TQFP PAG 64 1000 346.0 346.0 41.0 MSC1210Y3PAGT TQFP PAG 64 250 346.0 346.0 41.0 MSC1210Y4PAGR TQFP PAG 64 1500 346.0 346.0 41.0 MSC1210Y4PAGT TQFP PAG 64 250 346.0 346.0 41.
MECHANICAL DATA MTQF006A – JANUARY 1995 – REVISED DECEMBER 1996 PAG (S-PQFP-G64) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 48 0,08 M 33 49 32 64 17 0,13 NOM 1 16 7,50 TYP Gage Plane 10,20 SQ 9,80 12,20 SQ 11,80 0,25 0,05 MIN 1,05 0,95 0°– 7° 0,75 0,45 Seating Plane 0,08 1,20 MAX 4040282 / C 11/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C.
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