Datasheet
#$
#$
#$$
SBAS317E − APRIL 2004 − REVISED MAY 2006
www.ti.com
83
Watchdog Timer (WDTCON)
7 6 5 4 3 2 1 0 Reset Value
SFR FFh EWDT DWDT RWDT WDCNT4 WDCNT3 WDCNT2 WDCNT1 WDCNT0 00h
EWDT Enable Watchdog (R/W).
bit 7 Write 1/Write 0 sequence sets the Watchdog Enable Counting bit.
DWDT Disable Watchdog (R/W).
bit 6 Write 1/Write 0 sequence clears the Watchdog Enable Counting bit.
RWDT Reset Watchdog (R/W).
bit 5 Write 1/Write 0 sequence restarts the Watchdog Counter.
WDCNT4−0 Watchdog Count (R/W).
bits 4−0 Watchdog expires in (WDCNT + 1) • HMSEC to (WDCNT + 2) • HMSEC, if the sequence is not asserted. There is
an uncertainty of 1 count.
NOTE: If HCR0.3 (EWDR) is set and the watchdog timer expires, a system reset is generated. If HCR0.3 (EWDR) is
cleared and the watchdog timer expires, an interrupt is generated (see Table 6).