Datasheet

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SBAS317E − APRIL 2004 − REVISED MAY 2006
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8
AC ELECTRICAL CHARACTERISTICS
(1)
: DV
DD
= 2.7V to 5.25V
MSC120x
PARAMETER CONDITION
MIN TYP MAX
UNITS
PHASE LOCK LOOP (PLL)
Input Frequency Range External Crystal/Clock Frequency (f
OSC
) 32.768 kHz
PLL LF Mode PLLDIV = 449 (default) 14.8 MHz
PLL HF Mode PLLDIV = 899 (must be set by user), DV
DD
= 5V 29.5 MHz
PLL Lock Time Within 1% 2 ms
INTERNAL OSCILLATOR (IO) See Typical Characteristics
IO LF Mode DV
DD
= 5V 14.8 MHz
IO HF Mode DV
DD
= 5V 29.5 MHz
IO Settling Time Within 1% 1 ms
(1)
Parameters are valid over operating temperature range, unless otherwise specified.
EXTERNAL CLOCK DRIVE CLK TIMING: SEE FIGURE 1
2.7V to 3.6V 4.75V to 5.25V
SYMBOL PARAMETER
MIN
MAX MIN MAX
UNITS
External Clock Mode
f
OSC
(1)
External Crystal Frequency (f
OSC
) 1 20 1 33 MHz
1/t
OSC
(1)
External Clock Frequency (f
OSC
) 0 20 0 33 MHz
f
OSC
(1)
External Ceramic Resonator Frequency (f
OSC
) 1 12 1 12 MHz
t
HIGH
High Time
(2)
15 10 ns
t
LOW
Low Time
(2)
15 10 ns
t
R
Rise Time
(2)
5 5 ns
t
F
Fall Time
(2)
5 5 ns
(1)
t
CLK
= 1/f
OSC
= one oscillator clock period for clock divider = 1.
(2)
These values are characterized but not 100% production tested.
t
R
t
HIGH
V
IH
V
IH
0.8V 0.8V
V
IH
V
IH
0.8V 0.8V
t
LOW
t
OSC
t
F
Figure 1. External Clock Drive CLK
SERIAL FLASH PROGRAMMING TIMING: SEE FIGURE 2
SYMBOL PARAMETER MIN MAX UNITS
t
RW
RST width 2 t
OSC
— ns
t
RRD
RST rise to P1.0 internal pull high — 5 µs
t
RFD
RST falling to CPU start — 18 ms
t
RS
Input signal to RST falling setup time t
OSC
— ns
t
RH
RST falling to P1.0 hold time 18 — ms
NOTE: P1.0 is internally pulled−up with ~11k
Ω
during RST high.
P1.0/PROG
RST
t
RFD
,t
RH
t
RS
t
RRD
t
RW
Figure 2. Serial Flash Programming Timing