Datasheet

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SBAS317E − APRIL 2004 − REVISED MAY 2006
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79
PSEN/ALE Select (PASEL)
7 6 5 4 3 2 1 0 Reset Value
SFR F2h PSEN4 PSEN3 PSEN2 PSEN1 PSEN0 0 0 0 00h
PSEN2−0 PSEN Mode Select. Defines the output on P3.6 in UAM or SFPM.
bits 7−3 00000: General-purpose I/O (default)
00001: SYSCLK
00011: Internal PSEN
(refer to Figure 5 for timing)
00101: Internal ALE (refer to Figure 5 for timing)
00111: f
OSC
(buffered XIN oscillator clock)
01001: Memory WR (MOVX write)
01011: T0 Out (overflow)
(1)
01101: T1 Out (overflow)
(1)
01111: f
MOD
(2)
10001: SYSCLK/2 (toggles on rising edge)
(2)
10011: Internal PSEN/2
(2)
10101: Internal ALE/2
(2)
10111: f
OSC
(2)
11001: Memory WR/2 (MOVX write)
(2)
11011: T0 Out/2 (overflow)
(2)
11101: T1 Out/2 (overflow)
(2)
11111: f
MOD
/2
(2)
(1)
One period of these signals equal to t
CLK
.
(2)
Duty cycle is 50%.
Phase Lock Loop Low (PLLL)
7 6 5 4 3 2 1 0 Reset Value
SFR F4h PLL7 PLL6 PLL5 PLL4 PLL3 PLL2 PLL1 PLL0 xxh
PLL7−0 PLL Counter Value Least Significant Bit.
bits 7−0 PLL Frequency = External Crystal Frequency • (PLL9:0 + 1).