Datasheet
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SBAS317E − APRIL 2004 − REVISED MAY 2006
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72
ADC Control 2 (ADCON2)
7 6 5 4 3 2 1 0 Reset Value
SFR DEh DR7 DR6 DR5 DR4 DR3 DR2 DR1 DR0 1Bh
DR7−0 Decimation Ratio LSB (refer to ADCON3, SFR DFh).
bits 7−0
ADC Control 3 (ADCON3)
7 6 5 4 3 2 1 0 Reset Value
SFR DFh — — — — — DR10 DR9 DR8 06h
DR10−8 Decimation Ratio Most Significant 3 Bits.
bits 2−0 The ADC output data rate is:
f
MOD
Decimation Ratio
where f
MOD
+
f
CLK
(
ACLK)1
)
@ 64
.
Accumulator (A or ACC)
7 6 5 4 3 2 1 0 Reset Value
SFR E0h ACC.7 ACC.6 ACC.5 ACC.4 ACC.3 ACC.2 ACC.1 ACC.0 00h
ACC.7−0 Accumulator. This register serves as the accumulator for arithmetic and logic operations.
bits 7−0