Datasheet

#$
#$
#$$
SBAS317E − APRIL 2004 − REVISED MAY 2006
www.ti.com
71
ADC Control 1 (ADCON1)
7 6 5 4 3 2 1 0 Reset Value
SFR DDh OF_UF POL SM1 SM0 — CAL2 CAL1 CAL0 00h
OF_UF Overflow/Underflow. If this bit is set, the data in the Summation register is invalid; either an overflow or underflow
bit 6 occurred. This bit is cleared by writing a ‘0’ to it.
POL Polarity. Polarity of the ADC result and Summation register.
bit 6 0 = Bipolar.
1 = Unipolar.
DIGITAL OUTPUT
(ADRESH:ADRESM:ADRESL)
POL ANALOG INPUT
MSC1200
MSC1201
MSC1202
(1)
+FSR 7FFFFFh 007FFFh
0
ZERO 000000h 000000h
0
−FSR 800000h FF8000h
+FSR FFFFFFh 00FFFFh
1
ZERO 000000h 000000h
1
−FSR 000000h 000000h
(1)
The MSC1202 ADC result is sign-extended into ADRESH.
SM1−0 Settling Mode. Selects the type of filter or auto-select which defines the digital filter settling characteristics.
bits 5−4
SM1 SM0 SETTLING MODE
0 0 Auto
0 1 Fast Settling Filter
1 0 Sinc
2
Filter
1 1 Sinc
3
Filter
CAL2−0 Calibration Mode Control Bits. Writing to this register initiates calibration.
bits 2−0
CAL2 CAL1 CAL0 CALIBRATION MODE
0 0 0 No Calibration (default)
0 0 1 Self-Calibration, Offset and Gain
0 1 0 Self-Calibration, Offset only
0 1 1 Self-Calibration, Gain only
1 0 0 System Calibration, Offset only (requires external signal)
1 0 1 System Calibration, Gain only (requires external signal)
1 1 0 Reserved
1 1 1 Reserved
NOTE
:
Read value—000b.