Datasheet

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SBAS317E − APRIL 2004 − REVISED MAY 2006
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58
Interrupt Enable (IE)
7 6 5 4 3 2 1 0 Reset Value
SFR A8h EA 0 0 ES0 ET1 EX1 ET0 EX0 00h
EA Global Interrupt Enable. This bit controls the global masking of all interrupts except those in AIE (SFR A6h).
bit 7 0: Disable interrupt sources. This bit overrides individual interrupt mask settings for this register.
1: Enable all individual interrupt masks. Individual interrupts in this register will occur if enabled.
ES0 Enable Serial Port 0 Interrupt. This bit controls the masking of the serial Port 0 interrupt.
bit 4 0: Disable all serial Port 0 interrupts.
1: Enable interrupt requests generated by the RI_0 (SCON0.0, SFR 98h) or TI_0 (SCON0.1, SFR 98h) flags.
ET1 Enable Timer 1 Interrupt. This bit controls the masking of the Timer 1 interrupt.
bit 3 0: Disable Timer 1 interrupt.
1: Enable interrupt requests generated by the TF1 flag (TCON.7, SFR 88h).
EX1 Enable External Interrupt 1. This bit controls the masking of external interrupt 1.
bit 2 0: Disable external interrupt 1.
1: Enable interrupt requests generated by the INT1
pin.
ET0 Enable Timer 0 Interrupt. This bit controls the masking of the Timer 0 interrupt.
bit 1 0: Disable all Timer 0 interrupts.
1: Enable interrupt requests generated by the TF0 flag (TCON.5, SFR 88h).
EX0 Enable External Interrupt 0. This bit controls the masking of external interrupt 0.
bit 0 0: Disable external interrupt 0.
1: Enable interrupt requests generated by the INT0
pin.