Datasheet

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SBAS317E − APRIL 2004 − REVISED MAY 2006
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56
Auxiliary Interrupt Enable (AIE)
7 6 5 4 3 2 1 0 Reset Value
SFR A6h ESEC ESUM EADC EMSEC EI2C ECNT EALV 0 00h
Interrupts are enabled by EICON.4 (SFR D8h). The other interrupts are controlled by the IE and EIE registers.
ESEC Enable Second System Timer Interrupt (lowest priority auxiliary interrupt).
bit 7 Write: Set mask bit for this interrupt; 0 = masked, 1 = enabled.
Read: Second Timer Interrupt mask.
ESUM Enable Summation Interrupt.
bit 6 Write: Set mask bit for this interrupt; 0 = masked, 1 = enabled.
Read: Summation Interrupt mask.
EADC Enable ADC Interrupt.
bit 5 Write: Set mask bit for this interrupt; 0 = masked, 1 = enabled.
Read: ADC Interrupt mask.
EMSEC Enable Millisecond System Timer Interrupt.
bit 4 Write: Set mask bit for this interrupt; 0 = masked, 1 = enabled.
Read: Millisecond System Timer Interrupt mask.
EI2C Enable I
2
C Start/Stop Bit.
bit 3 Write: Set mask bit for this interrupt; 0 = masked, 1 = enabled.
Read: I
2
C Start/Stop Bit mask.
ECNT Enable Serial Bit Count Interrupt.
bit 2 Write: Set mask bit for this interrupt; 0 = masked, 1 = enabled.
Read: Serial Bit Count Interrupt mask.
EALV Enable Analog Low Voltage Interrupt.
bit 1 Write: Set mask bit for this interrupt; 0 = masked, 1 = enabled.
Read: Analog Low Voltage Detect Interrupt mask.