Datasheet

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SBAS317E − APRIL 2004 − REVISED MAY 2006
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54
I
2
C Control (I2CCON)
7 6 5 4 3 2 1 0 Reset Value
SFR 9Ah SBIT3 SBIT2 SBIT1 SBIT0 STOP START DCS CNTSEL 00h
SBIT3−0 Serial Bit Count. Number of bits transferred (read-only).
bits 7−4
SBIT3:0 COUNT
0x00 0
0x01 1
0x03 2
0x02 3
0x06 4
0x07 5
0x05 6
0x04 7
0x0C 8
STOP Stop-Bit Status.
bit 3 0: No stop
1: Stop condition received and I2C (bit 3, SFR A7h) set (cleared on write to I2CDATA)
START Start-Bit Status.
bit 2 0: No stop
1: Start or repeated start condition received and I2C (bit 3, SFR A7h) set (cleared on write to I2CDATA)
DCS Disable Serial Clock Stretch.
bit 1 0: Enable SCL stretch (cleared by firmware or START condition)
1: Disable SCL stretch
CNTSEL Counter Select.
bit 0 0: Counter IRQ set for bit counter = 8 (default)
1: Counter IRQ set for bit counter = 1
SPI Data (SPIDATA) / I
2
C Data (I2CDATA)
7 6 5 4 3 2 1 0 Reset Value
SFR 9Bh 00h
SPIDATA SPI Data. Data for SPI is read from or written to this location. The SPI transmit and receive buffers are
bits 7−0 separate registers, but both are addressed at this location. Read to clear the receive interrupt and write to clear the
transmit interrupt.
I2CDATA I2C Data. Data for I
2
C is read from or written to this location. The I
2
C transmit and receive buffers are
bits 7−0 separate registers, but both are addressed at this location.