Datasheet

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SBAS317E − APRIL 2004 − REVISED MAY 2006
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53
Serial Data Buffer 0 (SBUF0)
7 6 5 4 3 2 1 0 Reset Value
SFR 99h 00h
SBUF0 Serial Data Buffer 0. Data for Serial Port 0 is read from or written to this location. The serial transmit and receive
bits 7−0 buffers are separate registers, but both are addressed at this location.
SPI Control (SPICON)
7 6 5 4 3 2 1 0 Reset Value
SFR 9Ah SBIT3 SBIT2 SBIT1 SBIT0 ORDER CPHA ESS CPOL 00h
SBIT3−0 Serial Bit Count. Number of bits transferred (read-only).
bits 7−4
SBIT3:0 COUNT
0x00 0
0x01 1
0x03 2
0x02 3
0x06 4
0x07 5
0x05 6
0x04 7
0x0C 8
ORDER Set Bit Order for Transmit and Receive.
bit 3 0: Most significant bits first
1: Least significant bBits first
CPHA Serial Clock Phase Control.
bit 2 0: Valid data starting from half SCK period before the first edge of SCK
1: Valid data starting from the first edge of SCK
ESS Enable Slave Select.
bit 1 0: SS
(P1.4) is configured as a general-purpose I/O (default).
1: SS (P1.4) is configured as SS for SPI mode. DOUT (P1.2) drives when SS is low, and DOUT (P1.2) is
high-impedance when SS is high.
CPOL Serial Clock Polarity.
bit 0 0: SCK idle at logic low
1: SCK idle at logic high